Fake merge (using 'ours' strategy) to make sure that commit 2710742b stays, since it is used by a BTrain-over-WR release.

The commit itself is already rebased onto proposed_master as 9b9625bb.

sim: SV BFM assignment to port does not need MODPORT, greatly reduces number of warnings in Modelsim

rtl/wbmaster32: fix a nasty freeze when accesses are very tightly spaced: CIDs should be also FIFOed!

The sizes of to_wb and from_wb fifo were reduced in commit 4a430afa from 512 to
128 words. However, almost_full thresholds were still set to 500. As the
result some of the requests were lost when fifo was full because this fact was
never signaled to the gn4124 chip.

This code uses Xilinx specific cores.
Since this repo is now automatically included by hdlmake, the
project needs to be disabled WITHIN gn4124 instead of outside it.

Note: To avoid host hang in case of access to un-mapped address
      and user logic not asserting ERR signal.

core: Add err, rty and int signals to the wishbone masters interfaces. Terminate wb cycle in case of err on csr wb bus.

Note: The wb crossbar asserts err in case of access to un-mapped address.
      Therefore to avoid host hang in case of access to un-mapped address,
      the wb cycle is terminated (and returns 0xFFFFFFFF in case of read cycle).

tx_error acts as the abort signal.