sim: added SystemVerilog BFM
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- hdl/gn4124core/sim/gn4124_bfm/Manifest.py 3 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/Manifest.py
- hdl/gn4124core/sim/gn4124_bfm/gn4124_bfm.svh 261 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/gn4124_bfm.svh
- hdl/gn4124core/sim/gn4124_bfm/gn412x_bfm.vhd 2922 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/gn412x_bfm.vhd
- hdl/gn4124core/sim/gn4124_bfm/mem_model.vhd 2324 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/mem_model.vhd
- hdl/gn4124core/sim/gn4124_bfm/textutil.vhd 744 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/textutil.vhd
- hdl/gn4124core/sim/gn4124_bfm/util.vhd 680 additions, 0 deletionshdl/gn4124core/sim/gn4124_bfm/util.vhd
hdl/gn4124core/sim/gn4124_bfm/Manifest.py
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hdl/gn4124core/sim/gn4124_bfm/gn4124_bfm.svh
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hdl/gn4124core/sim/gn4124_bfm/gn412x_bfm.vhd
0 → 100644
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hdl/gn4124core/sim/gn4124_bfm/mem_model.vhd
0 → 100644
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hdl/gn4124core/sim/gn4124_bfm/textutil.vhd
0 → 100644
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hdl/gn4124core/sim/gn4124_bfm/util.vhd
0 → 100644
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