Merge master into develop: it includes Tomasz Wlostowski's SystemVerilog model for gn4124 (8de877b5) · Commits · Projects / Gennum GN4124 core · GitLab

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Gennum GN4124 core
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8de877b5

Commit 8de877b5 authored 9 years ago by

Javier D. Garcia-Lasheras

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Merge master into develop: it includes Tomasz Wlostowski's SystemVerilog model for gn4124

parents 834f488f ffea5479

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hdl/gn4124core/sim/gn4124_bfm/Manifest.py 3 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/Manifest.py
hdl/gn4124core/sim/gn4124_bfm/gn4124_bfm.svh 261 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/gn4124_bfm.svh
hdl/gn4124core/sim/gn4124_bfm/gn412x_bfm.vhd 2922 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/gn412x_bfm.vhd
hdl/gn4124core/sim/gn4124_bfm/mem_model.vhd 2324 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/mem_model.vhd
hdl/gn4124core/sim/gn4124_bfm/textutil.vhd 744 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/textutil.vhd
hdl/gn4124core/sim/gn4124_bfm/util.vhd 680 additions, 0 deletions

hdl/gn4124core/sim/gn4124_bfm/util.vhd

with 6934 additions and 0 deletions

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