Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

common/gc_i2c_slave: added option to allow automatic ACK of address byte without external user intervention

gc_frequency_meter: use gc_pulse_synchronizer for external PPS pulse (in case the measured frequency is slower than the gating frequency)

Lucas Russo authored 8 years ago and Maciej Lipinski committed 8 years ago

Signed-off-by: Maciej Lipinski <maciej.lipinski@cern.ch>

It seems that similar modules might be needed in other designs. The
added gc_async_signals_input_stage provides:
- synchronisation of input digital asynchronous pulses with the clock
- degliching (filter len config through generic)
- single-clock pulse generation
- extended pulses generation (config through generic)

The new gc_single_reset_gen can generate a single reset signal that
is synchronous with the system clock domain (input clk). The input
to the module is a vector of asynchronous reset signals, such as
PCIe reset or button. These input signals are synchronised with
the clock domain. Additionally, the powerup count-down is taken care
for by the module. The resulting single reset signal is passed through
a programmable number of flip-flops at the output (g_out_reg_depth)
so that the ISE optimizer has easier work with the global reset
funout.

This module is a generalized and (hopefully) improved version of the
spec_reset_gen.vhd that is copy+pasted into many SPEC-based designed.
It was suggested during a review of one of such designes that this
reset should be added to general-cores. This is the execution of this
feedback.

This module might be potentially integrated with the other available
reset-generation module (gc_reset.vhd).

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;

Use a counter instead of a shift register + comparator.

It is based on gc_glitch_filt, but with the glitch filter length
dynamically progammable via a port.

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

To make the design more modular, moved the synchronization chain out of
the gc_glitch_filt component. Made the necessary changes in the
components using the gc_glitch_filt.

Also added gc_glitch_filt documentation.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- I2C slave component now samples SDA line one rising SCL and changes
states and shifts out bits on its falling edge
- I2C slave component has clearer status outputs
- bridge component changed to reflect changes in I2C slave interface
- bridge component also returns to IDLE state on I2C stop condition, as
reflected by the I2C slave

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- gc_i2c_slave     -- generic I2C slave to be used with a processor or tied to a
                      Wishbone interface
- gc_glitch_filter -- glitch filter with selectable number of taps
- wb_i2c_bridge    -- I2C bridge implementing the protocol defined with ELMA
                      for monitoring VME crates
- wb_xil_multiboot -- module that accesses the Spartan-6 configuration logic
                      for reconfiguring the FPGA using MultiBoot

Doc files for each of these modules can be found in the doc/ folder.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>