Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Re-written the manifest to automatically detect ISE installation directory and add the IP files of blk_mem_generator/fifo_generator to the project being synthesized.

Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Added:
- asynchronous SRAM bus -> Wishbone bridge (wb_async_bridge)
- Conmax interconnect (wb_conmax)
- GPIO port (wb_gpio_port)
- Very simple timer (wb_simple timer)
- Simple UART (wb_uart)
- Vectored Interrupt controller (wb_vic)
- Virtual UART (mmapped FIFO, wb_virtual_uart)
- wbgen2 core generator libraries (wbgen2)

Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.