Replaced by a function taking the number of bits in parameter and returning a vector.

On Altera, "" generates a null-range warning.
When the dpram is used heavily, these warnings add up to many.

The RW ordering on address conflict varies by platform.
Some platforms only support some options.
Most of the dprams in WR are portable and don't depend on the order.
This new option allows a core to specify that it does not care what
the result of a RW conflict is, and thus work on more platforms.

For Xilinx, "dont_care" = "read_first", the old default.

On both Altera and Xilinx, a dual port memory can achieve twice the
bit-width per memory block when there is a single reader and writer.
This adds a place-holder generic_simple_dpram for Xilinx so that code
using the purpose-built variant for Altera continues to work on ISE.

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.

genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values

Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.

Quartus will not process a 'file_open' call during synthesis,
so we can instead initialize the RAM with a vhdl constant.

genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values