This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".

The previous implementation was introducing latches to the GN4124 core under Xilinx ISE.

Tested and verified to work with the following SPEC-based reference designs:
 - WR
 - MT
 - WRTD

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.