The WB master interface has been re-written, in order to improve performance, compatibility with the
"standard" and code readability.

The new interface has been successfully verified with existing testbenches from the following
projects:

* wr-cores
* wr-switch-hdl
* mockturtle
* ddr3-sp6-core
* fmc-adc-100m14b4cha

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.

This commit does three changes to gc_sync_word_wr:

1. It converts it to use internally gc_pulse_synchroniser2
2. It introduces a new "busy" output bit
3. It introduces a new generic, g_AUTO_WR which instructs the core to write a new word continously, without input from the user.