[sim] rewrite of the WB master interface

The WB master interface has been re-written, in order to improve performance, compatibility with the
"standard" and code readability.

The new interface has been successfully verified with existing testbenches from the following
projects:

* wr-cores
* wr-switch-hdl
* mockturtle
* ddr3-sp6-core
* fmc-adc-100m14b4cha

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>