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Created with Raphaël 2.2.015Dec142123Nov84310Oct7Sep110Aug83229Jul282520181628Jun2231May1222Mar1325Feb1711310Jan16Dec26Oct130Sep292823Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sepdsp: testbench for gc_cordicdsp/gc_cordic: fix translation errors introduced while porting the design from VEmodules/dsp: a collection of simple DSP cores from the SY-RF-FB's CommonVisual library.axi4_pkg: Added missing AxPROT fields + fixed WSTRB length in AXI4-Full record typedefstom-mr-axi-pack…tom-mr-axi-package-fixesaxi4_pkg: increase address with to 64 bits in AXI4-full record typedefsaxi4_pkg: declare AXI4 burst type constantsaxi4_pkg: define default 512-bit AXI4-Full master output constantsim: updated license headerstom-mr-sv-sim-r…tom-mr-sv-sim-reworktestbench: update SV Manifests to reflect changes in the naming/files of simulation packagestestbench: added .gitignoresim: provide legacy 'simdrv_defs' header for limited backward compatibilitysim: removed duplicate Wishbone definitions headersim: follow up with the API changes in CWishboneAccessor classsim: regenerated PWM & UART IP registers for SV simulation modelssim: Redesign and cleanup of the common SystemVerilog testing code:Merge branch '33-tools-generate-version-information-in-gen_sourceid-py' into 'master'tools: add version info from tag to gen_sourceid.pytools: add a couple of missing newlines to gen_sourceid.py outputtools: add comment to gen_sourceid.py explaining difference with gen_buildinfo.pyMerge branch 'proposed_master'Fix the tab spaces in various Testbench filesFix the tab spaces in gc_delay_genxwb_lm32_mcs: implement firmware preloading using generic_dpram_splittom-ucc-virtex5tom-ucc-virtex5genrams: declare generic_dpram_split component in the genram_pkg packagemodules/genrams/generic/ added wrappers for SystemVerilogmodules/wishbone/wb_spi/ added wrappers for SystemVerilogcommon: add gc_dec_8b10b and gc_enc_8b10b to Manifest.pygsi_master_get_…gsi_master_get_back_on_trackMerge branch 'master' of ssh://ohwr.org:7999/project/general-cores into gsi_master_get_back_on_trackmodules/wishbone/wb_spi/ added additional control register bit for using I/O data pinUse `$(shell pwd)` when defining a variable with a PATHsoftware, {spi, i2c}: gitignore: update list of files to be ignoredsoftware: {spi,i2c,htvic} Makefile: Rename variable 'LINUX' to 'KERNELSRC'common Manifest.py: removed gc_dec_8b10b.vhd and gc_enc_8b10b.vhdwrpc5 update: merged proposed_master into gsi_master_get_back_on_trackFixed an issue where the "RESPONSE_READ" was skipped.Minor fixes in some Common CoresTestbench added for Common core. Makefile and .yml file added to run CI for Gateware SimulationsTestbench added for genram coresTestbench added for wishbone coresTestbench added for AXI cores