* Only allocate FIFO space when a new operation is issued
  * Remove watchdog timeout which can violate WB signalling

  * MSI and PCI interrupts in the altera mega-function
  * Restructure master/slave registers for bridge to be more
    readable regarding which address takes which action
  * Receive wishbone operations and use them to pulse interrupts
  * Added registers to indicate the address/data from WB

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.

Due to the way Altera uses padding, it is not possible to eliminate it without
the full state recovered during TLP decoding. Therefore, this version moves
the padding handling after the 64-32 conversion.

Furthermore, the decoding of TLP records now follows the PCIe 3.0 standard
instead of the slim Altera documentation. All incoming TLP formats should be
correctly processed without losing synchronization.

Must detect BAR change during address decode.

stub wishbone device added for testing

Implement a wishbone streaming interface bridge from the Avalon RX stream

Add driver stub code