- Mar 06, 2012
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Wesley W. Terpstra authored
manual -- configure bus_end directly layout -- configure bus_end from nested bus layout ... and fix a bug where the dpram size was incorrect
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
Fixup bad addressing with a warning.
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Wesley W. Terpstra authored
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- Mar 05, 2012
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
Ensure the SDWB ROM fits into the crossbar bus_end and is aligned. Remove c_bus_bits which kept appearing where c_bus_end should have.
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Wesley W. Terpstra authored
Eliminate warning about constant zero. Use the aliases generic array.
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Wesley W. Terpstra authored
record count is 16 bit index aliased decription (to avoid overflow) Added feature: make it easy to relocate a device to a new address Checks added: confirm address ranges to not overlap during synthesis check wbd_begin/end addresses for compatability with the crossbar
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Wesley W. Terpstra authored
Decode the SDWB blocks to create bus addresses in the sdwb_crossbar. I still need to add assertions to confirm the user didn't give bad inputs.
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- Mar 02, 2012
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Wesley W. Terpstra authored
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- Feb 09, 2012
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Tomasz Wlostowski authored
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- Jan 31, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Jan 24, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values
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Tomasz Wlostowski authored
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- Jan 17, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Jan 16, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Nov 04, 2011
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Signed-off-by:
Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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Improve timings: Make all MUXs explicitly log deep Add a Kogge-Stone OR network for arbitration (makes arbitration scale log(n) with n masters, not O(n)) Signed-off-by:
Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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- Nov 02, 2011
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Tomasz Wlostowski authored
wishbone/wb_slave_adapter: prevents a pipelined master from chaging data/addr lines when talking to classic slave
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Tomasz Wlostowski authored
wishbone/xwb_bus_fanout: now determines the number of peripheral select bits from number of connected peripherals
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Tomasz Wlostowski authored
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Signed-off-by:
Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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Signed-off-by:
Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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Make the error device a completely standard wishbone device; we don't need high performance segfaults. Clearer is better. Signed-off-by:
Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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