testbench/wishbone: added testbench for wb_xilinx_fpga_loader

testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py

+action = "simulation"
+
+fetchto="../../../ip_cores"
+
+modules = { "local" :  "../../../" };
+
+files = ["main.sv", "SIM_CONFIG_S6_SERIAL.v", "glbl.v" ]
+
+vlog_opt= "+incdir+../../../sim"
\ No newline at end of file

testbench/wishbone/wb_xilinx_fpga_loader/glbl.v

+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule

testbench/wishbone/wb_xilinx_fpga_loader/main.sv

+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"
+
+`include "regs/xloader_regs.vh"
+
+module main;
+
+   reg clk_sys=1, rst_n=0;
+
+   always
+     #5ns clk_sys <= ~clk_sys;
+
+   initial begin 
+      repeat(5) @(posedge clk_sys);
+      rst_n <= 1;
+   end
+   
+
+   IWishboneMaster #(32, 32) U_WB
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+
+   wire cclk, din, program_b, init_b, done, suspend;
+   wire [1:0] m;
+   
+   wb_xilinx_fpga_loader DUT 
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i   (rst_n),
+
+      .wb_adr_i (U_WB.master.adr),
+      .wb_dat_i (U_WB.master.dat_o),
+      .wb_dat_o (U_WB.master.dat_i),
+      .wb_cyc_i (U_WB.master.cyc),
+      .wb_stb_i (U_WB.master.stb),
+      .wb_we_i  (U_WB.master.we),
+      .wb_ack_o (U_WB.master.ack),
+      .wb_sel_i (U_WB.master.sel),
+
+      .xlx_cclk_o      (cclk),
+      .xlx_din_o       (din),
+      .xlx_program_b_o (program_b),
+      .xlx_init_b_i     (init_b),
+      .xlx_done_i       (done),
+      .xlx_suspend_o (suspend),
+     
+      .xlx_m_o (m)
+      );
+   
+   
+   SIM_CONFIG_S6_SERIAL2
+  #(
+    .DEVICE_ID(32'h34000093) // xc6slx150t
+    ) U_serial_sim 
+    (
+     .DONE(done),
+     .CCLK(cclk),
+     .DIN(din),
+     .INITB(init_b), 
+     .M(m),
+     .PROGB(program_b)
+     );
+
+   task load_bitstream(CBusAccessor acc, string filename);
+      int f,i;
+      uint64_t csr;
+      
+     
+      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );
+      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);
+      f  = $fopen(filename, "r");
+      
+      while(!$feof(f))
+        begin
+           uint64_t rval;
+           acc.read(`ADDR_XLDR_FIFO_CSR, rval);
+           
+           if(!(rval&`XLDR_FIFO_CSR_FULL)) begin
+              int n;
+              bit [31:0] word;
+              
+              n  = $fread(word, f);
+              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));
+              acc.write(`ADDR_XLDR_FIFO_R1, word);
+              end
+        end
+
+      $fclose(f);
+
+      while(1) begin
+         acc.read( `ADDR_XLDR_CSR, csr);
+         if(csr & `XLDR_CSR_DONE) begin
+            $display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));
+            break;
+         end
+      end
+   endtask
+   
+   
+   initial begin
+      CBusAccessor acc;
+      int i;
+      
+      #1000ns;
+      acc = U_WB.get_accessor();
+
+      /* Load a sample spartan-6 bitstream */
+
+      load_bitstream(acc, "sample_bitstream/crc_gen.bin");
+      $stop;
+     
+   end // initial begin
+   
+endmodule // main
+

testbench/wishbone/wb_xilinx_fpga_loader/run.do

+make
+
+vsim work.main -voptargs="+acc"
+
+do wave.do
+run 30ms
+wave zoomfull
+radix -hex
\ No newline at end of file

testbench/wishbone/wb_xilinx_fpga_loader/sample_bitstream/Manifest.py

+target = "xilinx"
+action = "synthesis"
+
+files = "crc_gen.vhd"
+
+syn_device = "xc6slx4"
+syn_grade = "-2"
+syn_package = "csg225"
+syn_top = "crc_gen"
+syn_project = "test.xise"

testbench/wishbone/wb_xilinx_fpga_loader/sample_bitstream/crc_gen.vhd

+----------------------------------------------------------------------
+----                                                              ----
+---- Ultimate CRC.                                                ----
+----                                                              ----
+---- This file is part of the ultimate CRC projectt               ----
+---- http://www.opencores.org/cores/ultimate_crc/                 ----
+----                                                              ----
+---- Description                                                  ----
+---- CRC generator/checker, parallel implementation.              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Geir Drange, gedra@opencores.org                           ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU General          ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.0 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU General Public License for more details.----
+----                                                              ----
+---- You should have received a copy of the GNU General           ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/gpl.txt                     ----
+----                                                              ----
+----------------------------------------------------------------------
+--
+-- CVS Revision History
+--
+-- $Log: ucrc_par.vhd,v $
+-- Revision 1.1  2005/05/09 15:58:38  gedra
+-- Parallel implementation
+--
+-- Modified by T.W. for use in WhiteRabbit endpoint
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity crc_gen is
+  generic (
+-- polynomial of our CRC generator
+    g_polynomial : std_logic_vector       := x"04C11DB7";
+-- initial (after-reset) value of CRC
+    g_init_value : std_logic_vector       := x"ffffffff";
+-- residual value of CRC when matched
+    g_residue    : std_logic_vector       := x"38fb2284";
+-- width of full data input word 
+    g_data_width : integer range 2 to 256 := 16;
+-- width of smaller-than-full data input word
+    g_half_width : integer range 2 to 256 := 8;
+-- use synchronous reset when 1
+    g_sync_reset : integer range 0 to 1   := 0;
+-- dual-width mode (g_data_width - wide input word when 1 and g_half_width input
+-- word when 0)
+    g_dual_width : integer range 0 to 1   := 0);  -- use sync./async reset
+  port (
+    clk_i  : in std_logic;              -- clock
+    rst_i  : in std_logic;              -- reset, active high
+    en_i   : in std_logic;              -- enable input, active high
+    half_i : in std_logic;              -- 1: input word has g_half_width bits
+                                        -- 0: input word has g_data_width bits
+
+    data_i : in std_logic_vector(g_data_width - 1 downto 0);  -- data input
+
+    match_o : out std_logic;            -- CRC match flag: 1 - CRC matches
+
+    crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));  -- CRC
+                                                                      -- output value
+end crc_gen;
+
+architecture rtl of crc_gen is
+
+  function f_reverse_vector (a : in std_logic_vector)
+    return std_logic_vector is
+    variable v_result : std_logic_vector(a'reverse_range);
+  begin
+    for i in a'range loop
+      v_result(i) := a(i);
+    end loop;
+    return v_result;
+  end;
+
+  constant msb      : integer                        := g_polynomial'length - 1;
+  constant init_msb : integer                        := g_init_value'length - 1;
+  constant p        : std_logic_vector(msb downto 0) := g_polynomial;
+  constant dw       : integer                        := g_data_width;
+  constant pw       : integer                        := g_polynomial'length;
+  type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
+  type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
+  signal crca       : fb_array;
+  signal da, ma     : dmsb_array;
+  signal crc, zero  : std_logic_vector(msb downto 0);
+  signal arst, srst : std_logic;
+
+  signal a, b    : std_logic_vector(g_polynomial'length - 1 downto 0);
+  signal data_i2 : std_logic_vector(15 downto 0);
+  signal en_d0   : std_logic;
+  signal half_d0 : std_logic;
+  signal crc_tmp : std_logic_vector(31 downto 0);
+  signal crc_int : std_logic_vector(31 downto 0);
+    
+
+    
+begin
+
+  a <= g_init_value;
+  b <= g_polynomial;
+
+-- Parameter checking: Invalid generics will abort simulation/synthesis
+  PCHK1 : if msb /= init_msb generate
+    process
+    begin
+      report "g_polynomial and g_init_value vectors must be equal length!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK1;
+
+  PCHK2 : if (msb < 3) or (msb > 31) generate
+    process
+    begin
+      report "g_polynomial must be of order 4 to 32!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK2;
+
+  PCHK3 : if p(0) /= '1' generate       -- LSB must be 1
+    process
+    begin
+      report "g_polynomial must have lsb set to 1!"
+        severity failure;
+      wait;
+    end process;
+  end generate PCHK3;
+
+  data_i2(15 downto 0) <= (data_i(7 downto 0) & data_i(15 downto 8));
+--  data_i2(15 downto 0) <= f_reverse_vector(data_i(15 downto 0));
+
+-- Generate vector of each data bit
+  CA : for i in 1 to dw generate        -- data bits
+    DAT : for j in 1 to msb generate
+      da(i)(j) <= data_i2(i - 1);
+    end generate DAT;
+  end generate CA;
+
+-- Generate vector of each CRC MSB
+  MS0 : for i in 1 to msb generate
+    ma(1)(i) <= crc(msb);
+  end generate MS0;
+  MSP : for i in 2 to dw generate
+    MSU : for j in 1 to msb generate
+      ma(i)(j) <= crca(i - 1)(msb);
+    end generate MSU;
+  end generate MSP;
+
+-- Generate feedback matrix
+  crca(1)(0)            <= da(1)(1) xor crc(msb);
+  crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
+  FB : for i in 2 to dw generate
+    crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
+    crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
+                             ((da(i) xor ma(i)) and p(msb downto 1));
+  end generate FB;
+
+-- Reset signal
+  SR : if g_sync_reset = 1 generate
+    srst <= rst_i;
+    arst <= '0';
+  end generate SR;
+  AR : if g_sync_reset = 0 generate
+    srst <= '0';
+    arst <= rst_i;
+  end generate AR;
+
+-- CRC process
+  crc_tmp <= f_reverse_vector(not crc);
+  crc_int <= crc_tmp(7 downto 0) & crc_tmp(15 downto 8) & crc_tmp(23 downto 16) & crc_tmp(31 downto 24);
+  zero  <= (others => '0');
+
+  crc_o <= crc_int;
+  
+  CRCP : process (clk_i, arst)
+  begin
+    if arst = '1' then                  -- async. reset
+      crc     <= g_init_value;
+      half_d0 <= '0';
+    elsif rising_edge(clk_i) then
+      if srst = '1' then                -- sync. reset
+        crc <= g_init_value;
+      elsif en_i = '1' then
+        
+        if(half_i = '1' and g_dual_width = 1) then
+          crc <= crca(g_half_width);
+        else
+          crc <= crca(g_data_width);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  match_gen : process (clk_i, arst)
+  begin
+    if arst = '1' then                  -- async. reset
+      match_o <= '0';
+      en_d0 <= '0';
+    elsif rising_edge(clk_i) then
+      if srst = '1' then                -- sync. reset
+        match_o <= '0';
+        en_d0 <= '0';
+      else
+        en_d0 <= en_i;
+
+        if(en_d0 = '1') then
+          if crc_int = g_residue then
+            match_o <= '1';
+          else
+            match_o <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  
+end rtl;
+

testbench/wishbone/wb_xilinx_fpga_loader/wave.do

+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/g_interface_mode
+add wave -noupdate /main/DUT/g_address_granularity
+add wave -noupdate /main/DUT/clk_sys_i
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/wb_cyc_i
+add wave -noupdate /main/DUT/wb_stb_i
+add wave -noupdate /main/DUT/wb_we_i
+add wave -noupdate /main/DUT/wb_adr_i
+add wave -noupdate /main/DUT/wb_sel_i
+add wave -noupdate /main/DUT/wb_dat_i
+add wave -noupdate /main/DUT/wb_dat_o
+add wave -noupdate /main/DUT/wb_ack_o
+add wave -noupdate /main/DUT/wb_stall_o
+add wave -noupdate /main/DUT/xlx_cclk_o
+add wave -noupdate /main/DUT/xlx_din_o
+add wave -noupdate /main/DUT/xlx_program_b_o
+add wave -noupdate /main/DUT/xlx_init_b_i
+add wave -noupdate /main/DUT/xlx_done_i
+add wave -noupdate /main/DUT/xlx_suspend_o
+add wave -noupdate /main/DUT/xlx_m_o
+add wave -noupdate /main/DUT/state
+add wave -noupdate /main/DUT/clk_div
+add wave -noupdate /main/DUT/tick
+add wave -noupdate /main/DUT/init_b_synced
+add wave -noupdate /main/DUT/done_synced
+add wave -noupdate /main/DUT/timeout_counter
+add wave -noupdate /main/DUT/wb_in
+add wave -noupdate /main/DUT/wb_out
+add wave -noupdate /main/DUT/regs_in
+add wave -noupdate /main/DUT/regs_out
+add wave -noupdate /main/DUT/d_data
+add wave -noupdate /main/DUT/d_size
+add wave -noupdate /main/DUT/d_last
+add wave -noupdate /main/DUT/bit_counter
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {211850000 ps} 0}
+configure wave -namecolwidth 226
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {3937501184 ps}