OHWR general-cores VHDL library -------------------------------- TEST RELEASE - NOT READY FOR USE!
Wesley W. Terpstra
authored
record count is 16 bit index aliased decription (to avoid overflow) Added feature: make it easy to relocate a device to a new address Checks added: confirm address ranges to not overlap during synthesis check wbd_begin/end addresses for compatability with the crossbar
| Name | Last commit | Last update |
|---|---|---|
| modules | ||
| sim | ||
| testbench/wishbone | ||
| .gitignore | ||
| Manifest.py | ||
| README |