This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.

This commit does three changes to gc_sync_word_wr:

1. It converts it to use internally gc_pulse_synchroniser2
2. It introduces a new "busy" output bit
3. It introduces a new generic, g_AUTO_WR which instructs the core to write a new word continously, without input from the user.

Maciej Lipinski authored 5 years ago and Dimitris Lampridis committed 5 years ago

This is needed for fixed-latency streamers. Module was written by Tom,
he added it to wr-cores whereas it belongs here, I've moved it.

hdl: add RLOC constraint to gc_sync_ffs in order to keep the two FFs as close as possible to each other