[hdl] rewrite gc_sync_ffs to use gc_sync and edge detectors internally

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

modules/common/gc_sync_ffs.vhd

@@ -31,69 +31,53 @@ entity gc_sync_ffs is
     g_sync_edge : string := "positive");
   port(
     clk_i    : in  std_logic;   -- clock from the destination clock domain
-    rst_n_i  : in  std_logic;   -- reset
+    rst_n_i  : in  std_logic;   -- async reset
     data_i   : in  std_logic;   -- async input
     synced_o : out std_logic;   -- synchronized output
     npulse_o : out std_logic;   -- negative edge detect output
     ppulse_o : out std_logic);  -- positive edge detect output
 end entity gc_sync_ffs;
 
--- make Altera Quartus quiet regarding unknown attributes:
--- altera message_off 10335
-
 architecture arch of gc_sync_ffs is
 
-  signal sync0, sync1, sync2 : std_logic;
-
-  signal gc_sync_ffs_in : std_logic;
-
-  attribute shreg_extract          : string;
-  attribute shreg_extract of sync0 : signal is "no";
-  attribute shreg_extract of sync1 : signal is "no";
-  attribute shreg_extract of sync2 : signal is "no";
-
-  attribute keep          : string;
-  attribute keep of sync0 : signal is "true";
-  attribute keep of sync1 : signal is "true";
-
-  attribute rloc          : string;
-  attribute rloc of sync0 : signal is "X0Y0";
-  attribute rloc of sync1 : signal is "X0Y0";
-
-  attribute keep of gc_sync_ffs_in : signal is "true";
-
-  attribute keep_hierarchy         : string;
-  attribute keep_hierarchy of arch : architecture is "true";
-
-  -- synchronizer attribute for Vivado
-  attribute ASYNC_REG          : string;
-  attribute ASYNC_REG of sync0 : signal is "true";
-  attribute ASYNC_REG of sync1 : signal is "true";
-  attribute ASYNC_REG of sync2 : signal is "true";
+  signal sync, npulse, ppulse : std_logic;
 
 begin
 
-  -- rename data_i to something we can use as wildcard
-  -- in timing constraints
-  gc_sync_ffs_in <= data_i;
+  cmp_gc_sync : entity work.gc_sync
+    generic map (
+      g_sync_edge => g_sync_edge)
+    port map (
+      clk_i     => clk_i,
+      rst_n_a_i => rst_n_i,
+      d_i       => data_i,
+      q_o       => sync);
+
+  cmp_gc_posedge : entity work.gc_posedge
+    port map (
+      clk_i   => clk_i,
+      rst_n_i => rst_n_i,
+      data_i  => sync,
+      pulse_o => ppulse);
+
+  cmp_gc_negedge : entity work.gc_negedge
+    port map (
+      clk_i   => clk_i,
+      rst_n_i => rst_n_i,
+      data_i  => sync,
+      pulse_o => npulse);
 
   sync_posedge : if (g_sync_edge = "positive") generate
     process(clk_i, rst_n_i)
     begin
       if(rst_n_i = '0') then
-        sync0    <= '0';
-        sync1    <= '0';
-        sync2    <= '0';
         synced_o <= '0';
         npulse_o <= '0';
         ppulse_o <= '0';
       elsif rising_edge(clk_i) then
-        sync0    <= gc_sync_ffs_in;
-        sync1    <= sync0;
-        sync2    <= sync1;
-        synced_o <= sync1;
-        npulse_o <= sync2 and not sync1;
-        ppulse_o <= not sync2 and sync1;
+        synced_o <= sync;
+        npulse_o <= npulse;
+        ppulse_o <= ppulse;
       end if;
     end process;
   end generate sync_posedge;
@@ -102,19 +86,13 @@ begin
     process(clk_i, rst_n_i)
     begin
       if(rst_n_i = '0') then
-        sync0    <= '0';
-        sync1    <= '0';
-        sync2    <= '0';
         synced_o <= '0';
         npulse_o <= '0';
         ppulse_o <= '0';
       elsif falling_edge(clk_i) then
-        sync0    <= gc_sync_ffs_in;
-        sync1    <= sync0;
-        sync2    <= sync1;
-        synced_o <= sync1;
-        npulse_o <= sync2 and not sync1;
-        ppulse_o <= not sync2 and sync1;
+        synced_o <= sync;
+        npulse_o <= npulse;
+        ppulse_o <= ppulse;
       end if;
     end process;
   end generate sync_negedge;