Quartus will not process a 'file_open' call during synthesis,
so we can instead initialize the RAM with a vhdl constant.

Updated uses of the wishbone_pkg to use Tom's naming conventions.
Added Manifests for the new files.

  manual -- configure bus_end directly
  layout -- configure bus_end from nested bus layout
... and fix a bug where the dpram size was incorrect

Fixup bad addressing with a warning.

Ensure the SDWB ROM fits into the crossbar bus_end and is aligned.
Remove c_bus_bits which kept appearing where c_bus_end should have.

Eliminate warning about constant zero.
Use the aliases generic array.

  record count is 16 bit
  index aliased decription (to avoid overflow)

Added feature:
  make it easy to relocate a device to a new address

Checks added:
  confirm address ranges to not overlap during synthesis
  check wbd_begin/end addresses for compatability with the crossbar

Decode the SDWB blocks to create bus addresses in the sdwb_crossbar.
I still need to add assertions to confirm the user didn't give bad inputs.

genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Improve timings: Make all MUXs explicitly log deep Add a Kogge-Stone OR network for arbitration (makes arbitration scale log(n) with n masters, not O(n))

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

wishbone/wb_slave_adapter: prevents a pipelined master from chaging data/addr lines when talking to classic slave