sim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interface

So that in one read access, the software can read both the status and
the value and can decide if the value is correct.  This avoids race
issues.

Simplify the code and avoid possible glitches.

Olof Kindgren authored 4 years ago and Tristan Gingold committed 4 years ago

The goal is to make sure that files in the common directory don't
depend on things defined elsewhere. With these changes, the only
remaining issue is gc_delay_line that uses generic_dpram from
genrams

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>

Fixes to the latest proposed_master merge

See merge request !11

1.1.1 - 2020-09-14
==================

Fixed
-----
- sw: fix SPI driver to update the spi_message->actual_length

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

The spi-ocore driver was not updating the actual_length field in the
spi_message structure. This field could be used by SPI users to see if
all bytes have been transferred.

In particular we found the problem because the m25p80 driver uses the
actual_length to determine if there are transmission errors (-EIO).

Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Marcus Comstedt authored 4 years ago and Tristan Gingold committed 4 years ago

The response should not be EXOKAY unless an atomic access is requested
by the master using the LOCK signals.  This bridge does not even
support atomic accesses (it's an AXI4-Lite slave and does not have the
LOCK signals) so it's required to respond OKAY even if the master
does attempt an atomic access (this is how the master knows that the
slave does not support atomic accesses).  The AXI4-Lite specification
clearly states that the EXOKAY response is not supported in AXI4-Lite.

Marcus Comstedt authored 4 years ago and Tristan Gingold committed 4 years ago

The BVALID signal must be asserted once the write operation is
completed.  The master is not required to assert BREADY before this
happens.  The old code happened to work if the master tied BREADY
high, which is allowed but not required.

Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago

Conflicts:
	modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd

Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago

wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)

Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together

1.1.0 - 2020-07-24
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.0

Added
-----
- hdl: New indirect wishbone master (driven by an address and data register).
- hdl: New memory wrapper for Cheby.
- hdl: Provide a simple vhdl package to generate WB transactions.
- hdl: New wb_xc7_fw_update module.
- bld: Introduce gen_sourceid.py script to generate a package with the source id.

Changed
-------
- bld: gen_buildinfo.py now adds tag and dirty flag.

Fixed
-----
- hdl: regression to gc_sync_ffs introduced by v1.0.4.
- hdl: add dummy generic to generic_dpram in altera.
- hdl: add missing generics to generic_sync_fifo in genram_pkg.
- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.