Merge tag 'v1.1.0' into proposed_master

1.1.0 - 2020-07-24
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.0

Added
-----
- hdl: New indirect wishbone master (driven by an address and data register).
- hdl: New memory wrapper for Cheby.
- hdl: Provide a simple vhdl package to generate WB transactions.
- hdl: New wb_xc7_fw_update module.
- bld: Introduce gen_sourceid.py script to generate a package with the source id.

Changed
-------
- bld: gen_buildinfo.py now adds tag and dirty flag.

Fixed
-----
- hdl: regression to gc_sync_ffs introduced by v1.0.4.
- hdl: add dummy generic to generic_dpram in altera.
- hdl: add missing generics to generic_sync_fifo in genram_pkg.
- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.

CHANGELOG.rst

@@ -9,17 +9,28 @@ Change Log
 - Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
 - Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
 
-Unreleased
-==========
-https://ohwr.org/project/general-cores/compare/master...proposed_master
+1.1.0 - 2020-07-24
+==================
+https://www.ohwr.org/project/general-cores/tags/v1.1.0
 
 Added
 -----
-- [hdl] New memory wrapper for Cheby
+- hdl: New indirect wishbone master (driven by an address and data register).
+- hdl: New memory wrapper for Cheby.
+- hdl: Provide a simple vhdl package to generate WB transactions.
+- hdl: New wb_xc7_fw_update module.
+- bld: Introduce gen_sourceid.py script to generate a package with the source id.
+
+Changed
+-------
+- bld: gen_buildinfo.py now adds tag and dirty flag.
 
 Fixed
 -----
-- [hdl] avoid f_log2() circular dependencies in gc_extend_pulse.
+- hdl: regression to gc_sync_ffs introduced by v1.0.4.
+- hdl: add dummy generic to generic_dpram in altera.
+- hdl: add missing generics to generic_sync_fifo in genram_pkg.
+- hdl: avoid f_log2() circular dependencies in gc_extend_pulse.
 
 
 1.0.4 - 2020-03-26

modules/genrams/common/inferred_sync_fifo.vhd

@@ -12,7 +12,7 @@
 -- - configurable full/empty/almost full/almost empty/word count signals
 --
 --------------------------------------------------------------------------------
--- Copyright CERN 2011-2018
+-- Copyright CERN 2011-2020
 --------------------------------------------------------------------------------
 -- Copyright and related rights are licensed under the Solderpad Hardware
 -- License, Version 2.0 (the "License"); you may not use this file except
@@ -38,6 +38,12 @@ entity inferred_sync_fifo is
     g_size       : natural;
     g_show_ahead : boolean := false;
 
+    -- Previously, the full flag was asserted at g_size-1 when using g_show_ahead.
+    -- The new implementation solves this. However, for backward compatibility,
+    -- the default is to still use the previous behaviour. Set this to false to
+    -- switch to the new one.
+    g_show_ahead_legacy_mode : boolean := true;
+
     -- Read-side flag selection
     g_with_empty        : boolean := true;   -- with empty flag
     g_with_full         : boolean := true;   -- with full flag
@@ -84,6 +90,12 @@ architecture syn of inferred_sync_fifo is
 
 begin  -- syn
 
+  legacy_mode_check: assert g_show_ahead = false or g_show_ahead_legacy_mode = false
+    report legacy_mode_check'instance_name & ": show-ahead enabled for sync FIFO in " &
+    "legacy mode. In this mode, the full flag is asserted at g_SIZE-1. if you want the " &
+    "full flag to be asserted at g_SIZE, then disable g_SHOW_AHEAD_LEGACY_MODE."
+    severity NOTE;
+
   we_int <= we_i and not full;
   rd_int <= rd_i and not empty;
 
@@ -135,7 +147,8 @@ begin  -- syn
     end if;
   end process;
 
-  gen_comb_flags_showahead : if(g_show_ahead = true) generate
+  gen_comb_flags_showahead_legacy : if g_show_ahead = true and
+                                      g_show_ahead_legacy_mode = true generate
 
     process(clk_i)
     begin
@@ -149,6 +162,34 @@ begin  -- syn
     end process;
     full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
 
+  end generate gen_comb_flags_showahead_legacy;
+
+  gen_comb_flags_showahead : if g_show_ahead = true and
+                               g_show_ahead_legacy_mode = false generate
+
+    process(clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if rst_n_i = '0' then
+          guard_bit <= '0';
+          empty     <= '1';
+        else
+          if wr_ptr = rd_ptr_muxed and guard_bit = '0' then
+            empty <= '1';
+          else
+            empty <= '0';
+          end if;
+          if(wr_ptr + 1 = rd_ptr and we_int = '1') then
+            guard_bit <= '1';
+          elsif(rd_i = '1') then
+            guard_bit <= '0';
+          end if;
+        end if;
+      end if;
+    end process;
+
+    full <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0';
+
   end generate gen_comb_flags_showahead;
 
   gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate

modules/genrams/generic/generic_sync_fifo.vhd

@@ -12,7 +12,7 @@
 -- - configurable full/empty/almost full/almost empty/word count signals
 --
 --------------------------------------------------------------------------------
--- Copyright CERN 2011-2018
+-- Copyright CERN 2011-2020
 --------------------------------------------------------------------------------
 -- Copyright and related rights are licensed under the Solderpad Hardware
 -- License, Version 2.0 (the "License"); you may not use this file except
@@ -38,7 +38,13 @@ entity generic_sync_fifo is
     g_size       : natural;
     g_show_ahead : boolean := false;
 
-    -- Read-side flag selection
+    -- Previously, the full flag was asserted at g_size-1 when using g_show_ahead.
+    -- The new implementation solves this. However, for backward compatibility,
+    -- the default is to still use the previous behaviour. Set this to false to
+    -- switch to the new one.
+    g_show_ahead_legacy_mode : boolean := true;
+
+      -- Read-side flag selection
     g_with_empty        : boolean := true;   -- with empty flag
     g_with_full         : boolean := true;   -- with full flag
     g_with_almost_empty : boolean := false;
@@ -76,6 +82,7 @@ architecture syn of generic_sync_fifo is
       g_data_width             : natural;
       g_size                   : natural;
       g_show_ahead             : boolean;
+      g_show_ahead_legacy_mode : boolean;
       g_with_empty             : boolean;
       g_with_full              : boolean;
       g_with_almost_empty      : boolean;
@@ -105,6 +112,7 @@ begin  -- syn
         g_data_width             => g_data_width,
         g_size                   => g_size,
         g_show_ahead             => g_show_ahead,
+        g_show_ahead_legacy_mode => g_show_ahead_legacy_mode,
         g_with_empty             => g_with_empty,
         g_with_full              => g_with_full,
         g_with_almost_empty      => g_with_almost_empty,

modules/genrams/genram_pkg.vhd

@@ -209,6 +209,7 @@ package genram_pkg is
       g_data_width             : natural;
       g_size                   : natural;
       g_show_ahead             : boolean := false;
+      g_show_ahead_legacy_mode : boolean := true;
       g_with_empty             : boolean := true;
       g_with_full              : boolean := true;
       g_with_almost_empty      : boolean := false;