record count is 16 bit
  index aliased decription (to avoid overflow)

Added feature:
  make it easy to relocate a device to a new address

Checks added:
  confirm address ranges to not overlap during synthesis
  check wbd_begin/end addresses for compatability with the crossbar

Decode the SDWB blocks to create bus addresses in the sdwb_crossbar.
I still need to add assertions to confirm the user didn't give bad inputs.

genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Improve timings: Make all MUXs explicitly log deep Add a Kogge-Stone OR network for arbitration (makes arbitration scale log(n) with n masters, not O(n))

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

wishbone/wb_slave_adapter: prevents a pipelined master from chaging data/addr lines when talking to classic slave

wishbone/xwb_bus_fanout: now determines the number of peripheral select bits from number of connected peripherals

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Make the error device a completely standard wishbone device;
we don't need high performance segfaults. Clearer is better.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

This bug allowed a high priority master to seize control of a lower priority master if:
1. The low priority master had control for exactly one cycle
2. Combinatorial crossbar mode was off

... this made it possible to "steal the ACK" of another device and cause the bus to stall.

This commit will be followed by a few others which also tidy up the code a
bit in a way that would have made this bug more obvious to a reviewer.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>