0 is impossible, since it is the interconnect record
=> use it instead

The subrange type might not be known in this context.
Fixes:
  wishbone_pkg.vhd:1379:26: object subtype is not locally static

Variable lengths might change; standard forbids length in a loop.
Fixes:
  wishbone_pkg.vhd:1576:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1613:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1734:30: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1771:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1806:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1817:16: universal integer bound must be numeric literal or attribute

The so-called "inferred_X_fifo" are basically generics fifos using
inferred rams blocks from altera or xilinx, depending the target
platform. That's why it makes more sense to move them to the "generic"
folder of genrams. This change forces to rename the "generic_X_fifo"
under "altera". Since these fifos are using the altera fifo  Megafunction,
are going to be called "altera_X_fifo". The Manifest has been changed accordingly.

PCIe must respond to reads within a fairly tight deadline.
If we allow too many enqueued operations, that deadline may be missed.
Using a smaller FIFO depth causes back-pressure on the PCIe bus, slowing the
request arrival rate and thus increasing the time a single WB op can take.

Concretely, this makes it possible to perform an SPI flash write within
the PCIe time limit.

If a Wishbone master lowers the cycle line before receiving its acks, it is
non-conforming.  However, it is probably a good idea to not let an honest
slave (whose ack then comes in outside of the cycle) be penalized for that
master's misbehaviour.

This small change ensures the FIFO does not leak space in this case.