Although not mentioned in section 5.2 of Wishbone B4 specification, when interfacing a pipelined
master to a standard slave, it is also necessary to make sure that if the slave asserts ACK/ERR/RTY
for more than one clock cycle (which a standard slave could do since, according to Rule 3.50 of
Wishbone B4, "the slave deasserts ACK/ERR/RTY in response to the negation of STB"), the master will
still only see a one cycle wide pulse.

wb_reg_link: add generics for instantiating wb adapters, since wb_reg_link works correctly only when used with pipelined wb interfaces

xwb_register_link: also register the CYC signal, otherwise STB remains active for one more cycle after CYC is dropped, which is not compliant with Wishbone

this is needed for VXS integration in which hdlmake is used to generate
a list of files used, these failes are alter copied to a Visual Elite
based project

hdl: add RLOC constraint to gc_sync_ffs in order to keep the two FFs as close as possible to each other

genram: automatically pad with zeroes when reading from a mem init file smaller than the memory itself