Commits · 065baec2c2dfb8a12fb309c0fe77c4291edd001a · Projects / Platform-independent core collection · GitLab

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Mar 28, 2012
- genrams/xilinx/generic_dpram.vhd: removed clock assignemnts (simulation issues) · 065baec2
  Tomasz Wlostowski authored 13 years ago
  
  065baec2
- genrams: wea_i/web_i must not be ignored in byte addressed mode · 12a9a27f
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  12a9a27f
- genrams: removed extra delays on clock lines causing simulation issues · edeeb01c
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  edeeb01c
- genrams: fixed wrong bwsel port size when data width is not a multiple of 8 · b5c3f067
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  b5c3f067
- genrams: new file loader (DPRAMs only) · 8e2be575
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  8e2be575
- removed references to common-components · 6bf86846
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  6bf86846
- modules/genrams: Added genrams library (initial commit) · fbac4470
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
```
Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.
```
  fbac4470