Commits · 065baec2c2dfb8a12fb309c0fe77c4291edd001a · Projects / Platform-independent core collection · GitLab

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Mar 28, 2012
- genrams/xilinx/generic_dpram.vhd: removed clock assignemnts (simulation issues) · 065baec2
  Tomasz Wlostowski authored 13 years ago
  
  065baec2
- genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused... · 2a9759aa
  Tomasz Wlostowski authored 13 years ago
```
genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values
```
  2a9759aa
- genrams: generic_shiftreg_fifo.vhd: added zero-ing on reset · 8fd1d7dc
  Tomasz Wlostowski authored 13 years ago
  
  8fd1d7dc
- genrams: changed empty port in generic_shiftreg_fifo to q_valid (it's a show-ahead FIFO) · 8c560613
  Tomasz Wlostowski authored 13 years ago
  
  8c560613
- genrams: added small synchronous shift register-based FIFO (generic_shiftreg_fifo) · 3f463fe5
  Tomasz Wlostowski authored 13 years ago
  
  3f463fe5
- genrams: now distinguishes between FIFOs for Virtex6/Spartan6 · 493c7cfa
  Tomasz Wlostowski authored 13 years ago
  
  493c7cfa
- modules/common: added clock rate independent pulse synchronizer (gc_pulse_synchronizer) · 6121b3c1
  Tomasz Wlostowski authored 13 years ago
  
  6121b3c1
- genrams: wea_i/web_i must not be ignored in byte addressed mode · 12a9a27f
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  12a9a27f
- genrams: removed extra delays on clock lines causing simulation issues · edeeb01c
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  edeeb01c
- genrams: disabled messages in memory_loader_pkg · f66ac9e2
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  f66ac9e2
- genrams: fixed wrong bwsel port size when data width is not a multiple of 8 · b5c3f067
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  b5c3f067
- genrams: new file loader (DPRAMs only) · 8e2be575
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  8e2be575
- genrams: now distinguishes between altera/xilinx functional models for simulation · 4afe89ad
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  4afe89ad
- genrams/xilinx: Check for XILINX environment variable, print an error if ISE not installed · 65f51f04
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  65f51f04
- genrams/altera: added Manifest · 85a67b9f
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  85a67b9f
- genrams/xilinx: fixed wrong data count port width in component declaration of fifo_gen. · 54ed25b0
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago
  
  54ed25b0
- removed references to common-components · 6bf86846
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
  
  6bf86846
- modules/genrams/xilinx: added missing files to the Manifest, test release for OHWR · df9a20e9
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
  
  df9a20e9
- modules/genrams: bugfixes in ISE core generator file import. · ac678060
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
  
  ac678060
- modules/genrams/Manifest.py: automatic import of Xilinx Core Generator cores · 65aa4680
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Re-written the manifest to automatically detect ISE installation directory and add the IP files of blk_mem_generator/fifo_generator to the project being synthesized.
```
  65aa4680
- modules/genrams: Added genrams library (initial commit) · fbac4470
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.
```
  fbac4470