lm32: add missing wires to silence warnings

In Verilog, an "assign x = y;" will cause a warning in Quartus if x was not defined.
For example,
  Warning (10236): Verilog HDL Implicit Net warning at lm32_allprofiles.v(45398): created implicit net for "multiply"
This patch defines all such nets.

Also, the CSR width is too narrow by default (CFG2 must fit).

modules/wishbone/wb_lm32/src/lm32_cpu.v

@@ -341,6 +341,9 @@ reg load_x;
 reg load_m;
 wire load_q_x;
 wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
 wire store_d;                                   // Indicates a store instruction
 reg store_x;
 reg store_m;
@@ -371,6 +374,7 @@ wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be sele
 wire x_result_sel_csr_d;                        // Select X stage result from CSRs
 reg x_result_sel_csr_x;
 `ifdef LM32_MC_ARITHMETIC_ENABLED
+wire q_d;
 wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
 reg x_result_sel_mc_arith_x;
 `endif
@@ -689,6 +693,8 @@ reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
 wire dc_ss;                                     // Is single-step enabled
 `endif
 wire dc_re;                                     // Remap all exceptions
+wire bp_match;
+wire wp_match;
 wire exception_x;                               // An exception occured in the X stage
 reg exception_m;                                // An instruction that caused an exception is in the M stage
 wire debug_exception_x;                         // Indicates if a debug exception has occured

modules/wishbone/wb_lm32/src/lm32_decoder.v

@@ -308,6 +308,77 @@ wire sign_extend_immediate;                     // Whether the immediate should
 wire select_high_immediate;                     // Whether to select the high immediate  
 wire select_call_immediate;                     // Whether to select the call immediate 
 
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_divu;
+`endif
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_modu;
+`endif
+`ifdef LM32_MULTIPLY_ENABLED
+wire op_mul;
+`endif
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire op_sextb;
+wire op_sexth;
+`endif
+wire op_sh;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire op_sl;
+`endif
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire shift;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire shift;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire sext;
+`endif
+
 /////////////////////////////////////////////////////
 // Functions
 /////////////////////////////////////////////////////
@@ -396,7 +467,7 @@ assign shift_right = op_sr | op_sru;
 `ifdef CFG_SIGN_EXTEND_ENABLED
 assign sext = op_sextb | op_sexth;
 `endif
-`ifdef LM32_MULTIPLY_ENABLED
+`ifdef CFG_MC_MULTIPLY_ENABLED
 assign multiply = op_mul;
 `endif
 `ifdef CFG_MC_DIVIDE_ENABLED

modules/wishbone/wb_lm32/src/lm32_include.v

@@ -183,7 +183,7 @@
 `define LM32_CSR_WIDTH                  4
 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
 `else
-`define LM32_CSR_WIDTH                  3
+`define LM32_CSR_WIDTH                  4 // CFG2 is "a"
 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
 `endif
 `endif

modules/wishbone/wb_lm32/src/lm32_interrupt.v

@@ -108,6 +108,9 @@ reg    [`LM32_WORD_RNG] csr_read_data;
 wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
 //p_ragma attribute asserted preserve_signal true
 wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
 
 // Interrupt CSRs