From 5eb407d8d1e279127eefe771948e5a63f668f65c Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Fri, 1 Mar 2013 11:42:08 +0100
Subject: [PATCH] lm32: add missing wires to silence warnings
In Verilog, an "assign x = y;" will cause a warning in Quartus if x was not defined.
For example,
Warning (10236): Verilog HDL Implicit Net warning at lm32_allprofiles.v(45398): created implicit net for "multiply"
This patch defines all such nets.
Also, the CSR width is too narrow by default (CFG2 must fit).
---
.../wb_lm32/generated/lm32_allprofiles.v | 13335 ++++++++--------
modules/wishbone/wb_lm32/src/lm32_cpu.v | 6 +
modules/wishbone/wb_lm32/src/lm32_decoder.v | 73 +-
modules/wishbone/wb_lm32/src/lm32_include.v | 2 +-
modules/wishbone/wb_lm32/src/lm32_interrupt.v | 3 +
5 files changed, 7072 insertions(+), 6347 deletions(-)
diff --git a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
index e59b37b1..9542aaa9 100644
--- a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+++ b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
@@ -53,16 +53,6 @@
-
-
-
-
-
-
-
-
-
-
@@ -88,12 +78,13 @@
-
+
+
+
+
-
-
-
+
@@ -231,25 +222,24 @@
-
-
-
+
+
-
-
-
+
+
+
@@ -352,47 +342,27 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
-
+
-
-
-
-
@@ -401,8 +371,6 @@
-
-
@@ -410,19 +378,28 @@
+
+
-
+
+
-
+
+
+
+
+
+
+
+
-
@@ -580,7 +557,7 @@
-module lm32_top_full_debug (
+module lm32_top_full (
clk_i,
rst_i,
@@ -737,15 +714,14 @@ wire [ (2-1):0] D_BTE_O;
-
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
-wire jtag_update;
-wire [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_q;
-wire jtck;
-wire jrstn;
+
+
+
+
+
+
+
@@ -824,7 +800,7 @@ endfunction
-lm32_cpu_full_debug cpu (
+lm32_cpu_full cpu (
.clk_i (clk_i),
@@ -845,13 +821,12 @@ lm32_cpu_full_debug cpu (
-
- .jtag_clk (jtck),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
-
+
+
+
+
+
@@ -880,10 +855,9 @@ lm32_cpu_full_debug cpu (
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d),
-
@@ -918,21 +892,20 @@ lm32_cpu_full_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
-jtag_cores jtag_cores (
+
- .reg_d (jtag_reg_d),
- .reg_addr_d (jtag_reg_addr_d),
+
+
- .reg_update (jtag_update),
- .reg_q (jtag_reg_q),
- .reg_addr_q (jtag_reg_addr_q),
- .jtck (jtck),
- .jrstn (jrstn)
- );
-
+
+
+
+
+
+
+
endmodule
@@ -1152,7 +1125,7 @@ endmodule
-
+
@@ -1304,7 +1277,7 @@ endmodule
-module lm32_mc_arithmetic_full_debug (
+module lm32_mc_arithmetic_full (
clk_i,
rst_i,
@@ -1833,7 +1806,7 @@ endmodule
-
+
@@ -1970,7 +1943,7 @@ endmodule
-module lm32_cpu_full_debug (
+module lm32_cpu_full (
clk_i,
@@ -1991,13 +1964,12 @@ module lm32_cpu_full_debug (
-
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
+
+
+
+
+
@@ -2026,10 +1998,9 @@ module lm32_cpu_full_debug (
+
+
- jtag_reg_d,
- jtag_reg_addr_d,
-
@@ -2070,9 +2041,8 @@ module lm32_cpu_full_debug (
parameter eba_reset = 32'h00000000;
+
-parameter deba_reset = 32'h10000000;
-
@@ -2108,11 +2078,11 @@ parameter dcache_limit = 32'h7fffffff;
+
-parameter watchpoints = 32'h4;
-
-
+parameter watchpoints = 0;
+
@@ -2154,12 +2124,11 @@ input [ (32-1):0] interrupt;
+
+
+
+
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
-
@@ -2199,12 +2168,11 @@ input D_RTY_I;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
-
@@ -2285,6 +2253,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -2316,6 +2287,7 @@ wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+wire q_d;
wire x_result_sel_mc_arith_d;
reg x_result_sel_mc_arith_x;
@@ -2384,15 +2356,14 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
+wire [ (4 -1):0] csr_d;
+reg [ (4 -1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
+
+
-wire break_d;
-reg break_x;
-
wire scall_d;
reg scall_x;
@@ -2405,16 +2376,14 @@ reg eret_m;
-
-wire bret_d;
-reg bret_x;
-wire bret_q_x;
-reg bret_m;
-
+
+
+
+
+
-
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -2620,32 +2589,25 @@ wire stall_wb_load;
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
+
+
+
-
-wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
-wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
-wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
-wire jtag_access_complete;
-
-
-wire jtag_break;
+
+
+
+
@@ -2678,9 +2640,8 @@ wire kill_w;
reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-
reg [ (3-1):0] eid_x;
@@ -2690,39 +2651,36 @@ reg [ (3-1):0] eid_x;
-
-
-
-wire dc_ss;
+
-wire dc_re;
-wire exception_x;
-reg exception_m;
-wire debug_exception_x;
-reg debug_exception_m;
-reg debug_exception_w;
-wire debug_exception_q_w;
-wire non_debug_exception_x;
-reg non_debug_exception_m;
-reg non_debug_exception_w;
-wire non_debug_exception_q_w;
+
+
+
+
+
+
+
+
+wire exception_x;
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+
-
-
-wire reset_exception;
+
+
-
@@ -2730,10 +2688,9 @@ wire interrupt_exception;
+
+
-wire breakpoint_exception;
-wire watchpoint_exception;
-
@@ -2817,7 +2774,7 @@ endfunction
-lm32_instruction_unit_full_debug #(
+lm32_instruction_unit_full #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -2876,12 +2833,11 @@ lm32_instruction_unit_full_debug #(
+
+
+
+
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
-
@@ -2917,10 +2873,9 @@ lm32_instruction_unit_full_debug #(
+
+
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
-
@@ -2936,7 +2891,7 @@ lm32_instruction_unit_full_debug #(
);
-lm32_decoder_full_debug decoder (
+lm32_decoder_full decoder (
.instruction (instruction_d),
@@ -3017,16 +2972,14 @@ lm32_decoder_full_debug decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
+
- .break_opcode (break_d),
-
.scall (scall_d),
.eret (eret_d),
+
- .bret (bret_d),
-
@@ -3036,7 +2989,7 @@ lm32_decoder_full_debug decoder (
);
-lm32_load_store_unit_full_debug #(
+lm32_load_store_unit_full #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -3172,7 +3125,7 @@ lm32_multiplier multiplier (
-lm32_mc_arithmetic_full_debug mc_arithmetic (
+lm32_mc_arithmetic_full mc_arithmetic (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -3211,7 +3164,7 @@ lm32_mc_arithmetic_full_debug mc_arithmetic (
-lm32_interrupt_full_debug interrupt_unit (
+lm32_interrupt_full interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -3220,18 +3173,17 @@ lm32_interrupt_full_debug interrupt_unit (
.stall_x (stall_x),
+
+
- .non_debug_exception (non_debug_exception_q_w),
- .debug_exception (debug_exception_q_w),
-
-
+ .exception (exception_q_w),
+
.eret_q_x (eret_q_x),
+
- .bret_q_x (bret_q_x),
-
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -3246,117 +3198,95 @@ lm32_interrupt_full_debug interrupt_unit (
-
-lm32_jtag_full_debug jtag (
+
- .clk_i (clk_i),
- .rst_i (rst_i),
+
+
- .jtag_clk (jtag_clk),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+
+
-
-
- .csr (csr_x),
- .csr_write_data (operand_1_x),
- .csr_write_enable (csr_write_enable_q_x),
- .stall_x (stall_x),
+
+
+
+
-
-
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
+
+
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+
-
-
- .jtx_csr_read_data (jtx_csr_read_data),
- .jrx_csr_read_data (jrx_csr_read_data),
+
+
-
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
+
+
+
+
+
+
+
-
-
- .jtag_break (jtag_break),
- .jtag_reset (reset_exception),
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d)
- );
-
-
-
-
-
-
-lm32_debug_full_debug #(
- .breakpoints (breakpoints),
- .watchpoints (watchpoints)
- ) hw_debug (
+
+
- .clk_i (clk_i),
- .rst_i (rst_i),
- .pc_x (pc_x),
- .load_x (load_x),
- .store_x (store_x),
- .load_store_address_x (adder_result_x),
- .csr_write_enable_x (csr_write_enable_q_x),
- .csr_write_data (operand_1_x),
- .csr_x (csr_x),
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
-
-
- .eret_q_x (eret_q_x),
- .bret_q_x (bret_q_x),
- .stall_x (stall_x),
- .exception_x (exception_x),
- .q_x (q_x),
- .dcache_refill_request (dcache_refill_request),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- .dc_ss (dc_ss),
+
+
+
+
+
+
+
- .dc_re (dc_re),
- .bp_match (bp_match),
- .wp_match (wp_match)
- );
-
@@ -3856,25 +3786,21 @@ assign kill_w = 1'b0
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
- )
- && (valid_x == 1'b1)
- )
-
-
- || (jtag_break == 1'b1)
+
+
+
+
+
+
+
+
- ;
-
+
-assign watchpoint_exception = wp_match == 1'b1;
-
@@ -3901,17 +3827,38 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
+
+
+
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
- ;
+
+
+
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
+
+
+
- || (reset_exception == 1'b1)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign exception_x = (system_call_exception == 1'b1)
|| (instruction_bus_error_exception == 1'b1)
@@ -3927,9 +3874,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
@@ -3941,55 +3887,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
;
-
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
always @(*)
begin
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+
+
-
-
- if (data_bus_error_exception == 1'b1)
- eid_x = 3'h4;
- else
+
+
+
+
+
+
+
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
- else
-
@@ -4002,11 +3920,10 @@ begin
+
+
+
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
-
@@ -4019,9 +3936,8 @@ begin
if ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
)
eid_x = 3'h6;
@@ -4058,19 +3974,18 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
+
+
+
+
+
+
+
+
+
+
+
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
- )
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
- )
- && (kill_d == 1'b0)
- )
-
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -4176,24 +4091,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
@@ -4204,13 +4116,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
-
+
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
@@ -4225,12 +4137,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
- 1'b1,
-
+ 1'b0,
+
+
@@ -4239,19 +4151,19 @@ assign cfg = {
-
- 1'b1,
-
-
-
- 1'b1,
+ 1'b0,
+
+
+ 1'b0,
+
+
1'b1,
@@ -4332,17 +4244,16 @@ assign cfg2 = {
assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
+ && (csr_d == 4 'h3)
&& (stall_d == 1'b0)
&& (kill_d == 1'b0)
&& (valid_d == 1'b1))
+
+
+
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
-
;
@@ -4350,21 +4261,20 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 5'h4))
+ && (csr_x == 4 'h4))
+
+
+
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h4))
-
;
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[ (4 -1):0];
always @(*)
@@ -4372,29 +4282,27 @@ begin
case (csr_x)
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 4 'h0,
+ 4 'h1,
+ 4 'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
+ 4 'h6: csr_read_data_x = cfg;
+ 4 'h7: csr_read_data_x = {eba, 8'h00};
+
- 5'h9: csr_read_data_x = {deba, 8'h00};
-
+
+
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
-
- 5'ha: csr_read_data_x = cfg2;
+ 4 'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -4411,37 +4319,33 @@ begin
eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
end
end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
- else
- begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
+
+
+
+
+
+
+
+
+
- end
-end
-
@@ -4623,7 +4527,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
+ csr_x <= { 4 {1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -4646,16 +4550,14 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
+
- break_x <= 1'b0;
-
scall_x <= 1'b0;
eret_x <= 1'b0;
+
- bret_x <= 1'b0;
-
@@ -4699,10 +4601,9 @@ begin
+
+
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
-
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -4714,13 +4615,13 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
-
+
+ exception_w <= 1'b0;
+
+
memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
@@ -4800,9 +4701,8 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
+
- break_x <= break_d;
-
scall_x <= scall_d;
@@ -4812,9 +4712,8 @@ begin
eret_x <= eret_d;
+
- bret_x <= bret_d;
-
write_enable_x <= write_enable_d;
end
@@ -4866,40 +4765,40 @@ begin
-
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
- else
- write_idx_m <= write_idx_x;
-
-
+
+
+
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else
+ write_idx_m <= write_idx_x;
+
+
condition_met_m <= condition_met_x;
+
+
+
+
+
+
+
+
+
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
- branch_target_m <= {deba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= {eba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= branch_target_x;
-
-
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+
@@ -4912,16 +4811,14 @@ begin
eret_m <= eret_q_x;
+
- bret_m <= bret_q_x;
-
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
+
- debug_exception_m <= debug_exception_x;
- non_debug_exception_m <= non_debug_exception_x;
-
end
@@ -4936,9 +4833,8 @@ begin
data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
+
- && (reset_exception == 1'b0)
-
;
@@ -4970,13 +4866,13 @@ begin
write_enable_w <= write_enable_m;
-
- debug_exception_w <= debug_exception_m;
- non_debug_exception_w <= non_debug_exception_m;
-
+
+ exception_w <= exception_m;
+
+
if ( (stall_m == 1'b0)
@@ -5384,7 +5280,7 @@ endmodule
-
+
@@ -5521,7 +5417,7 @@ endmodule
-module lm32_load_store_unit_full_debug (
+module lm32_load_store_unit_full (
clk_i,
rst_i,
@@ -5899,7 +5795,7 @@ endfunction
-lm32_dcache_full_debug #(
+lm32_dcache_full #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -6616,7 +6512,7 @@ endmodule
-
+
@@ -6851,7 +6747,7 @@ endmodule
-module lm32_decoder_full_debug (
+module lm32_decoder_full (
instruction,
@@ -6932,16 +6828,14 @@ module lm32_decoder_full_debug (
bi_conditional,
bi_unconditional,
+
- break_opcode,
-
scall,
eret,
+
- bret,
-
@@ -7077,20 +6971,18 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-output break_opcode;
-wire break_opcode;
+
+
output scall;
wire scall;
output eret;
wire eret;
-
-output bret;
-wire bret;
+
+
@@ -7112,6 +7004,92 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+wire op_divu;
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+wire op_modu;
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -7269,9 +7247,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -7454,16 +7431,14 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
+
-assign break_opcode = op_raise & ~instruction[2];
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
+
-assign bret = op_b & (instruction[25:21] == 5'd31);
-
@@ -7717,7 +7692,7 @@ endmodule
-
+
@@ -7895,7 +7870,7 @@ endmodule
-module lm32_icache_full_debug (
+module lm32_icache_full (
clk_i,
rst_i,
@@ -8565,7 +8540,7 @@ endmodule
-
+
@@ -8741,7 +8716,7 @@ endmodule
-module lm32_dcache_full_debug (
+module lm32_dcache_full (
clk_i,
rst_i,
@@ -9461,7 +9436,7 @@ endmodule
-
+
@@ -9597,106 +9572,133 @@ endmodule
+
+
+
+
+
+
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-module lm32_debug_full_debug (
-
- clk_i,
- rst_i,
- pc_x,
- load_x,
- store_x,
- load_store_address_x,
- csr_write_enable_x,
- csr_write_data,
- csr_x,
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
-
+
+
-
- eret_q_x,
- bret_q_x,
- stall_x,
- exception_x,
- q_x,
-
- dcache_refill_request,
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- dc_ss,
+
+
- dc_re,
- bp_match,
- wp_match
- );
+
+
+
+
+
-parameter breakpoints = 0;
-parameter watchpoints = 0;
+
+
+
+
-input clk_i;
-input rst_i;
+
+
+
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-input load_x;
-input store_x;
-input [ (32-1):0] load_store_address_x;
-input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
+
+
+
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
-
+
+
+
+
+
-input eret_q_x;
-input bret_q_x;
-input stall_x;
-input exception_x;
-input q_x;
-
-input dcache_refill_request;
-
@@ -9705,52 +9707,177 @@ input dcache_refill_request;
-
-output dc_ss;
-reg dc_ss;
+
+
+
+
+
+
+
+
+
+
-output dc_re;
-reg dc_re;
-output bp_match;
-wire bp_match;
-output wp_match;
-wire wp_match;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-genvar i;
+
+
+
+
+
+
+
+
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
-reg bp_e[0:breakpoints-1];
-wire [0:breakpoints-1]bp_match_n;
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
-wire [0:watchpoints]wp_match_n;
-wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
-
-reg [ 2:0] state;
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -9775,245 +9902,6 @@ reg [ 2:0] state;
-
-
-
-
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
-
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
-
-
-
-
-
-
-
-
-
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
- end
-endgenerate
-generate
-
-
- if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
- else
-assign bp_match = state == 3'b011;
-
-
-
-
-
-
-
-endgenerate
-
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_comb
-assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
- end
-endgenerate
-generate
- if (watchpoints > 0)
-assign wp_match = |wp_match_n;
- else
-assign wp_match = 1'b0;
-endgenerate
-
-
-
-
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
-
-
-
-
-
-
-
-
-
-
-
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
- begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
- bp_e[i] <= debug_csr_write_data[0];
- end
- end
-end
- end
-endgenerate
-
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
- end
- else
- begin
- if (debug_csr_write_enable == 1'b1)
- begin
- if (debug_csr == 5'h8)
- wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
- wp[i] <= debug_csr_write_data;
- end
- end
-end
- end
-endgenerate
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- dc_re <= debug_csr_write_data[1];
- end
-end
-
-
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 3'b000;
- dc_ss <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- begin
- dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
- else
- state <= 3'b001;
- end
- case (state)
- 3'b001:
- begin
-
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
- )
- && (stall_x == 1'b0)
- )
- state <= 3'b010;
- end
- 3'b010:
- begin
-
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
- end
- 3'b011:
- begin
-
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
-
-
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- begin
- dc_ss <= 1'b0;
- state <= 3'b100;
- end
- end
- 3'b100:
- begin
-
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
-
-
- state <= 3'b000;
- end
- endcase
- end
-end
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -10231,7 +10119,7 @@ endmodule
-
+
@@ -10368,7 +10256,7 @@ endmodule
-module lm32_instruction_unit_full_debug (
+module lm32_instruction_unit_full (
clk_i,
rst_i,
@@ -10421,12 +10309,11 @@ module lm32_instruction_unit_full_debug (
+
+
+
+
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
-
@@ -10462,10 +10349,9 @@ module lm32_instruction_unit_full_debug (
+
+
- jtag_read_data,
- jtag_access_complete,
-
@@ -10555,12 +10441,11 @@ input i_rty_i;
+
+
+
+
-input jtag_read_enable;
-input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
@@ -10601,11 +10486,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
+
-reg [ (32-1):0] i_dat_o;
-
-
+wire [ (32-1):0] i_dat_o;
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -10613,21 +10498,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
+
-reg [ (4-1):0] i_sel_o;
-
-
+wire [ (4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
+
-reg i_we_o;
-
-
+wire i_we_o;
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -10639,12 +10524,11 @@ wire [ (2-1):0] i_bte_o;
+
+
+
+
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
-output jtag_access_complete;
-wire jtag_access_complete;
-
@@ -10710,9 +10594,8 @@ reg bus_error_f;
+
-reg jtag_access;
-
@@ -10830,7 +10713,7 @@ endfunction
-lm32_icache_full_debug #(
+lm32_icache_full #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -10953,11 +10836,11 @@ assign instruction_f = icache_data_f;
-
-
-
-
+assign i_dat_o = 32'd0;
+assign i_we_o = 1'b0;
+assign i_sel_o = 4'b1111;
+
assign i_bte_o = 2'b00;
@@ -11074,18 +10957,17 @@ end
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
-always @(*)
-begin
- case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
- endcase
-end
+
+
+
+
+
+
+
+
+
+
@@ -11110,11 +10992,10 @@ begin
+
+
+
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
-
end
else
@@ -11127,16 +11008,15 @@ begin
if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
+
+
+
+
+
+
+
+
- if (jtag_access == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
- end
- else
-
begin
if (last_word == 1'b1)
@@ -11169,10 +11049,9 @@ begin
if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
- i_sel_o <= 4'b1111;
-
+
+
+
i_adr_o <= {first_address, 2'b00};
i_cyc_o <= 1'b1;
@@ -11186,27 +11065,26 @@ begin
end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- else
- begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
- begin
- case (jtag_address[1:0])
- 2'b00: i_sel_o <= 4'b1000;
- 2'b01: i_sel_o <= 4'b0100;
- 2'b10: i_sel_o <= 4'b0010;
- 2'b11: i_sel_o <= 4'b0001;
- endcase
- i_adr_o <= jtag_address;
- i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
- end
- end
-
@@ -11546,7 +11424,7 @@ endmodule
-
+
@@ -11681,523 +11559,443 @@ endmodule
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-module lm32_jtag_full_debug (
- clk_i,
- rst_i,
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
-
- csr,
- csr_write_enable,
- csr_write_data,
- stall_x,
+
+
+
+
+
+
+
+
+
+
-
-
- jtag_read_data,
- jtag_access_complete,
+
+
-
-
- exception_q_w,
-
-
- jtx_csr_read_data,
- jrx_csr_read_data,
+
+
+
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
+
+
+
+
+
+
+
-
-
- jtag_break,
- jtag_reset,
+
+
- jtag_reg_d,
- jtag_reg_addr_d
- );
-
+
+
+
-input clk_i;
-input rst_i;
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
+
+
-
+
+
+
+
-input [ (5-1):0] csr;
-input csr_write_enable;
-input [ (32-1):0] csr_write_data;
-input stall_x;
+
+
+
+
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+
+
-
-
-input exception_q_w;
+
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
-
-
-output jtag_csr_write_enable;
-reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
-output jtag_read_enable;
-reg jtag_read_enable;
-output jtag_write_enable;
-reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-output jtag_break;
-reg jtag_break;
-output jtag_reset;
-reg jtag_reset;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
+
+
+
+
-reg rx_update;
-reg rx_update_r;
-reg rx_update_r_r;
-reg rx_update_r_r_r;
-
+
+
+
+
-wire [ 7:0] rx_byte;
-wire [2:0] rx_addr;
+
-
-reg [ 7:0] uart_tx_byte;
-reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
-reg uart_rx_valid;
-
+
+
+
+
+
-reg [ 3:0] command;
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+
+
+
+
+
+
+
-reg [ 3:0] state;
-
+
-
-assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
-assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_write_data = jtag_byte_4;
+
+
+
+
-
-
-assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
+
+
-
+
-assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+
+
-assign rx_byte = jtag_reg_q;
-assign rx_addr = jtag_reg_addr_q;
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- rx_update <= 1'b0;
- rx_update_r <= 1'b0;
- rx_update_r_r <= 1'b0;
- rx_update_r_r_r <= 1'b0;
- end
- else
- begin
- rx_update <= jtag_update;
- rx_update_r <= rx_update;
- rx_update_r_r <= rx_update_r;
- rx_update_r_r_r <= rx_update_r_r;
- end
-end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'h0;
- command <= 4'b0000;
- jtag_reg_d <= 8'h00;
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
-
-
+
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+
+
+
+
+
+
+
+
+
-
-
- uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
- uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
+
+
- end
- else
- begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
- begin
- case (csr)
- 5'he:
- begin
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
- end
- 5'hf:
- begin
+
+
+
+
+
- uart_rx_valid <= 1'b0;
- end
- endcase
- end
-
-
-
-
+
+
+
- if (exception_q_w == 1'b1)
- begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
- end
+
+
+
+
+
+
+
- case (state)
- 4'h0:
- begin
+
+
+
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- command <= rx_byte[7:4];
- case (rx_addr)
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 3'b000:
- begin
- case (rx_byte[7:4])
-
+
+
+
+
+
+
+
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
- end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 5;
- end
- 4'b0101:
- state <= 4'h1;
-
+
- 4'b0110:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
- jtag_break <= 1'b1;
- end
- 4'b0111:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
+
+
+
+
+
+
+
+
+
- jtag_reset <= 1'b1;
- end
- endcase
- end
+
+
+
+
+
-
-
+
+
- 3'b001:
- begin
- uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
- end
- 3'b010:
- begin
- jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
- end
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- default:
- ;
- endcase
- end
- end
- 4'h1:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_0 <= rx_byte;
- state <= 4'h2;
- end
- end
- 4'h2:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_1 <= rx_byte;
- state <= 4'h3;
- end
- end
- 4'h3:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_2 <= rx_byte;
- state <= 4'h4;
- end
- end
- 4'h4:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
- else
- state <= 4'h5;
- end
- end
- 4'h5:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_4 <= rx_byte;
- state <= 4'h6;
- end
- end
- 4'h6:
- begin
- case (command)
- 4'b0001,
- 4'b0011:
- begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0010,
- 4'b0100:
- begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0101:
- begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
- end
- endcase
- end
- 4'h7:
- begin
- if (jtag_access_complete == 1'b1)
- begin
- jtag_read_enable <= 1'b0;
- jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
- end
- 4'h8:
- begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
-
- endcase
- end
-end
-
-endmodule
-
@@ -12415,7 +12213,7 @@ endmodule
-
+
@@ -12552,7 +12350,7 @@ endmodule
-module lm32_interrupt_full_debug (
+module lm32_interrupt_full (
clk_i,
rst_i,
@@ -12561,18 +12359,17 @@ module lm32_interrupt_full_debug (
stall_x,
-
- non_debug_exception,
- debug_exception,
-
+
+
+ exception,
+
eret_q_x,
+
- bret_q_x,
-
csr,
csr_write_data,
@@ -12601,21 +12398,20 @@ input [interrupts-1:0] interrupt;
input stall_x;
+
+
-input non_debug_exception;
-input debug_exception;
-
-
+input exception;
+
input eret_q_x;
+
-input bret_q_x;
-
-input [ (5-1):0] csr;
+input [ (4 -1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -12636,15 +12432,17 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
reg ie;
reg eie;
+
-reg bie;
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -12664,11 +12462,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
- bie,
-
+
+ 1'b0,
+
eie,
ie
@@ -12682,19 +12480,19 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
+ 4 'h2: csr_read_data = ip;
+ 4 'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -12705,18 +12503,18 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
+ 4 'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -12745,9 +12543,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -12759,21 +12556,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -12781,6 +12570,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -12798,28 +12595,26 @@ always @(posedge clk_i )
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h1)
+ if (csr == 4 'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12836,9 +12631,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -12848,21 +12642,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -12870,6 +12656,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -12885,26 +12679,24 @@ always @(posedge clk_i )
end
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12971,6 +12763,8 @@ endmodule
+
+
@@ -12996,19 +12790,26 @@ endmodule
-
-
-
-
+
+
-
-
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -13140,24 +12941,25 @@ endmodule
-
+
+
-
-
+
+
+
+
-
-
@@ -13260,24 +13062,36 @@ endmodule
-
-
+
+
+
+
+
+
+
+
+
+
-
+
-
+
+
+
+
+
@@ -13287,6 +13101,8 @@ endmodule
+
+
@@ -13295,29 +13111,28 @@ endmodule
+
+
-
-
+
-
-
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
+
@@ -13475,7 +13290,7 @@ endmodule
-module lm32_top_full (
+module lm32_top_full_debug (
clk_i,
rst_i,
@@ -13632,14 +13447,15 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
-
-
-
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+
@@ -13718,7 +13534,7 @@ endfunction
-lm32_cpu_full cpu (
+lm32_cpu_full_debug cpu (
.clk_i (clk_i),
@@ -13739,12 +13555,13 @@ lm32_cpu_full cpu (
-
-
-
-
-
+
+ .jtag_clk (jtck),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
@@ -13773,9 +13590,10 @@ lm32_cpu_full cpu (
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d),
+
@@ -13810,20 +13628,21 @@ lm32_cpu_full cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
+
+jtag_cores jtag_cores (
-
-
-
-
-
-
-
-
+ .reg_d (jtag_reg_d),
+ .reg_addr_d (jtag_reg_addr_d),
-
+ .reg_update (jtag_update),
+ .reg_q (jtag_reg_q),
+ .reg_addr_q (jtag_reg_addr_q),
+ .jtck (jtck),
+ .jrstn (jrstn)
+ );
+
endmodule
@@ -14043,7 +13862,7 @@ endmodule
-
+
@@ -14195,7 +14014,7 @@ endmodule
-module lm32_mc_arithmetic_full (
+module lm32_mc_arithmetic_full_debug (
clk_i,
rst_i,
@@ -14724,7 +14543,7 @@ endmodule
-
+
@@ -14861,7 +14680,7 @@ endmodule
-module lm32_cpu_full (
+module lm32_cpu_full_debug (
clk_i,
@@ -14882,12 +14701,13 @@ module lm32_cpu_full (
-
-
-
-
-
+
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
@@ -14916,9 +14736,10 @@ module lm32_cpu_full (
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d,
+
@@ -14959,8 +14780,9 @@ module lm32_cpu_full (
parameter eba_reset = 32'h00000000;
-
+parameter deba_reset = 32'h10000000;
+
@@ -14996,11 +14818,11 @@ parameter dcache_limit = 32'h7fffffff;
-
-
-parameter watchpoints = 0;
+parameter watchpoints = 32'h4;
+
+
@@ -15042,11 +14864,12 @@ input [ (32-1):0] interrupt;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
@@ -15086,11 +14909,12 @@ input D_RTY_I;
-
-
-
-
+output [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
@@ -15171,6 +14995,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -15202,6 +15029,7 @@ wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+wire q_d;
wire x_result_sel_mc_arith_d;
reg x_result_sel_mc_arith_x;
@@ -15270,14 +15098,15 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (5-1):0] csr_d;
+reg [ (5-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
-
-
+wire break_d;
+reg break_x;
+
wire scall_d;
reg scall_x;
@@ -15290,14 +15119,16 @@ reg eret_m;
-
-
-
-
-
+
+wire bret_d;
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+
+
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -15503,25 +15334,32 @@ wire stall_wb_load;
-
-
-
-
-
-
-
-
+
+wire [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
+
-
-
+wire jtag_csr_write_enable;
+wire [ (32-1):0] jtag_csr_write_data;
+wire [ (5-1):0] jtag_csr;
+wire jtag_read_enable;
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
-
+
+
+wire jtag_break;
+
+
@@ -15554,8 +15392,9 @@ wire kill_w;
reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+
reg [ (3-1):0] eid_x;
@@ -15565,34 +15404,41 @@ reg [ (3-1):0] eid_x;
-
-
-
-
-
-
-
+
+
+wire dc_ss;
+
+wire dc_re;
+wire bp_match;
+wire wp_match;
+wire exception_x;
+reg exception_m;
+wire debug_exception_x;
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
-
+
-wire exception_x;
-reg exception_m;
-reg exception_w;
-wire exception_q_w;
-
+
-
-
+wire reset_exception;
+
+
@@ -15600,9 +15446,10 @@ wire interrupt_exception;
-
-
+wire breakpoint_exception;
+wire watchpoint_exception;
+
@@ -15686,7 +15533,7 @@ endfunction
-lm32_instruction_unit_full #(
+lm32_instruction_unit_full_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -15745,11 +15592,12 @@ lm32_instruction_unit_full #(
-
-
-
-
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+
@@ -15785,9 +15633,10 @@ lm32_instruction_unit_full #(
-
-
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+
@@ -15803,7 +15652,7 @@ lm32_instruction_unit_full #(
);
-lm32_decoder_full decoder (
+lm32_decoder_full_debug decoder (
.instruction (instruction_d),
@@ -15884,14 +15733,16 @@ lm32_decoder_full decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+ .break_opcode (break_d),
+
.scall (scall_d),
.eret (eret_d),
-
+ .bret (bret_d),
+
@@ -15901,7 +15752,7 @@ lm32_decoder_full decoder (
);
-lm32_load_store_unit_full #(
+lm32_load_store_unit_full_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -16037,7 +15888,7 @@ lm32_multiplier multiplier (
-lm32_mc_arithmetic_full mc_arithmetic (
+lm32_mc_arithmetic_full_debug mc_arithmetic (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -16076,7 +15927,7 @@ lm32_mc_arithmetic_full mc_arithmetic (
-lm32_interrupt_full interrupt_unit (
+lm32_interrupt_full_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -16085,17 +15936,18 @@ lm32_interrupt_full interrupt_unit (
.stall_x (stall_x),
-
-
-
- .exception (exception_q_w),
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+
+
.eret_q_x (eret_q_x),
-
+ .bret_q_x (bret_q_x),
+
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -16110,95 +15962,117 @@ lm32_interrupt_full interrupt_unit (
-
+
+lm32_jtag_full_debug jtag (
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
-
-
-
-
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
-
-
-
-
+
+
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
-
-
+
+
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
+
+
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
-
-
+
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
-
-
-
-
-
-
-
+
+
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
-
-
-
-
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+
-
-
-
-
+
+lm32_debug_full_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
-
-
-
-
-
-
-
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .pc_x (pc_x),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_store_address_x (adder_result_x),
+ .csr_write_enable_x (csr_write_enable_q_x),
+ .csr_write_data (operand_1_x),
+ .csr_x (csr_x),
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
-
-
-
-
-
-
-
+
+
+ .eret_q_x (eret_q_x),
+ .bret_q_x (bret_q_x),
+ .stall_x (stall_x),
+ .exception_x (exception_x),
+ .q_x (q_x),
+
+
+ .dcache_refill_request (dcache_refill_request),
+
-
-
-
-
-
+
+ .dc_ss (dc_ss),
+
+
+ .dc_re (dc_re),
+ .bp_match (bp_match),
+ .wp_match (wp_match)
+ );
+
@@ -16698,21 +16572,25 @@ assign kill_w = 1'b0
-
-
-
-
-
-
-
-
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
+ )
+ && (valid_x == 1'b1)
+ )
+
+ || (jtag_break == 1'b1)
+
+
+ ;
+
-
+assign watchpoint_exception = wp_match == 1'b1;
+
@@ -16739,38 +16617,17 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
-
-
-
-
-
-
-
-
-
-
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
+ ;
-
-
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+
+ || (reset_exception == 1'b1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign exception_x = (system_call_exception == 1'b1)
|| (instruction_bus_error_exception == 1'b1)
@@ -16786,8 +16643,9 @@ assign exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
@@ -16799,27 +16657,55 @@ assign exception_x = (system_call_exception == 1'b1)
;
+
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
always @(*)
begin
+
+
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
-
-
-
-
-
-
+
-
-
-
+ if (data_bus_error_exception == 1'b1)
+ eid_x = 3'h4;
+ else
+
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
+ else
+
@@ -16832,10 +16718,11 @@ begin
-
-
-
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
+
@@ -16848,8 +16735,9 @@ begin
if ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
)
eid_x = 3'h6;
@@ -16886,18 +16774,19 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
-
-
-
-
-
-
-
-
-
-
-
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
+ )
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
+ )
+ && (kill_d == 1'b0)
+ )
+
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -17003,21 +16892,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
@@ -17028,12 +16920,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
@@ -17049,19 +16941,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
-
-
@@ -17070,11 +16955,18 @@ assign cfg = {
+
+ 1'b1,
+
- 1'b0,
+
+
+ 1'b1,
+
+
@@ -17156,16 +17048,17 @@ assign cfg2 = {
assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 3'h3)
+ && (csr_d == 5'h3)
&& (stall_d == 1'b0)
&& (kill_d == 1'b0)
&& (valid_d == 1'b1))
-
-
-
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
+
;
@@ -17173,20 +17066,21 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 3'h4))
+ && (csr_x == 5'h4))
-
-
-
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h4))
+
;
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (5-1):0];
always @(*)
@@ -17194,27 +17088,29 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
-
+ 5'h9: csr_read_data_x = {deba, 8'h00};
+
-
-
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
+
- 3'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -17231,33 +17127,37 @@ begin
eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
end
end
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ end
+end
+
@@ -17439,7 +17339,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 5{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -17462,14 +17362,16 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
-
+ break_x <= 1'b0;
+
scall_x <= 1'b0;
eret_x <= 1'b0;
-
+ bret_x <= 1'b0;
+
@@ -17513,9 +17415,10 @@ begin
-
-
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
+
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -17527,12 +17430,12 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
-
-
- exception_w <= 1'b0;
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
+
+
@@ -17613,8 +17516,9 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+ break_x <= break_d;
+
scall_x <= scall_d;
@@ -17624,8 +17528,9 @@ begin
eret_x <= eret_d;
-
+ bret_x <= bret_d;
+
write_enable_x <= write_enable_d;
end
@@ -17677,40 +17582,40 @@ begin
+
-
-
-
-
-
-
-
-
- if (exception_x == 1'b1)
+ if (non_debug_exception_x == 1'b1)
write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
+
+
+
+
+
condition_met_m <= condition_met_x;
-
-
-
-
-
-
-
-
-
-
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
+ branch_target_m <= {deba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= {eba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= branch_target_x;
+
+
@@ -17723,14 +17628,16 @@ begin
eret_m <= eret_q_x;
-
+ bret_m <= bret_q_x;
+
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ debug_exception_m <= debug_exception_x;
+ non_debug_exception_m <= non_debug_exception_x;
+
end
@@ -17745,8 +17652,9 @@ begin
data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
-
+ && (reset_exception == 1'b0)
+
;
@@ -17778,12 +17686,12 @@ begin
write_enable_w <= write_enable_m;
-
-
-
- exception_w <= exception_m;
+ debug_exception_w <= debug_exception_m;
+ non_debug_exception_w <= non_debug_exception_m;
+
+
@@ -18192,7 +18100,7 @@ endmodule
-
+
@@ -18329,7 +18237,7 @@ endmodule
-module lm32_load_store_unit_full (
+module lm32_load_store_unit_full_debug (
clk_i,
rst_i,
@@ -18707,7 +18615,7 @@ endfunction
-lm32_dcache_full #(
+lm32_dcache_full_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -19424,7 +19332,7 @@ endmodule
-
+
@@ -19659,7 +19567,7 @@ endmodule
-module lm32_decoder_full (
+module lm32_decoder_full_debug (
instruction,
@@ -19740,14 +19648,16 @@ module lm32_decoder_full (
bi_conditional,
bi_unconditional,
-
+ break_opcode,
+
scall,
eret,
-
+ bret,
+
@@ -19883,18 +19793,20 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+output break_opcode;
+wire break_opcode;
+
output scall;
wire scall;
output eret;
wire eret;
-
-
+output bret;
+wire bret;
+
@@ -19916,6 +19828,92 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+wire op_divu;
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+wire op_modu;
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -20073,9 +20071,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -20258,14 +20255,16 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+assign break_opcode = op_raise & ~instruction[2];
+
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+assign bret = op_b & (instruction[25:21] == 5'd31);
+
@@ -20519,7 +20518,7 @@ endmodule
-
+
@@ -20697,7 +20696,7 @@ endmodule
-module lm32_icache_full (
+module lm32_icache_full_debug (
clk_i,
rst_i,
@@ -21367,7 +21366,7 @@ endmodule
-
+
@@ -21543,7 +21542,7 @@ endmodule
-module lm32_dcache_full (
+module lm32_dcache_full_debug (
clk_i,
rst_i,
@@ -22263,7 +22262,7 @@ endmodule
-
+
@@ -22399,314 +22398,160 @@ endmodule
-
-
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
+
-
-
-
-
-
+
-
-
+module lm32_debug_full_debug (
+
+ clk_i,
+ rst_i,
+ pc_x,
+ load_x,
+ store_x,
+ load_store_address_x,
+ csr_write_enable_x,
+ csr_write_data,
+ csr_x,
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+
+
-
-
+ eret_q_x,
+ bret_q_x,
+ stall_x,
+ exception_x,
+ q_x,
+
-
-
-
-
-
-
-
+ dcache_refill_request,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+ dc_ss,
-
-
-
+ dc_re,
+ bp_match,
+ wp_match
+ );
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+parameter breakpoints = 0;
+parameter watchpoints = 0;
+input clk_i;
+input rst_i;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input load_x;
+input store_x;
+input [ (32-1):0] load_store_address_x;
+input csr_write_enable_x;
+input [ (32-1):0] csr_write_data;
+input [ (5-1):0] csr_x;
+
+input jtag_csr_write_enable;
+input [ (32-1):0] jtag_csr_write_data;
+input [ (5-1):0] jtag_csr;
+
+input eret_q_x;
+input bret_q_x;
+input stall_x;
+input exception_x;
+input q_x;
+
-
-
-
-
-
-
-
-
-
-
+input dcache_refill_request;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+output dc_ss;
+reg dc_ss;
+
+output dc_re;
+reg dc_re;
+output bp_match;
+wire bp_match;
+output wp_match;
+wire wp_match;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+genvar i;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg bp_e[0:breakpoints-1];
+wire [0:breakpoints-1]bp_match_n;
-
+reg [ 1:0] wpc_c[0:watchpoints-1];
+reg [ (32-1):0] wp[0:watchpoints-1];
+wire [0:watchpoints]wp_match_n;
+wire debug_csr_write_enable;
+wire [ (32-1):0] debug_csr_write_data;
+wire [ (5-1):0] debug_csr;
+
-
-
-
-
-
-
-
-
-
+reg [ 2:0] state;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
@@ -22729,6 +22574,247 @@ endmodule
+
+
+
+
+
+
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+ end
+endgenerate
+generate
+
+
+ if (breakpoints > 0)
+assign bp_match = (|bp_match_n) || (state == 3'b011);
+ else
+assign bp_match = state == 3'b011;
+
+
+
+
+
+
+
+endgenerate
+
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+ end
+endgenerate
+generate
+ if (watchpoints > 0)
+assign wp_match = |wp_match_n;
+ else
+assign wp_match = 1'b0;
+endgenerate
+
+
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
+
+
+
+
+
+
+
+
+
+
+
+
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ begin
+ bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_e[i] <= debug_csr_write_data[0];
+ end
+ end
+end
+ end
+endgenerate
+
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ wp[i] <= { 32{1'bx}};
+ wpc_c[i] <= 2'b00;
+ end
+ else
+ begin
+ if (debug_csr_write_enable == 1'b1)
+ begin
+ if (debug_csr == 5'h8)
+ wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+ if (debug_csr == 5'h18 + i)
+ wp[i] <= debug_csr_write_data;
+ end
+ end
+end
+ end
+endgenerate
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ dc_re <= debug_csr_write_data[1];
+ end
+end
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 3'b000;
+ dc_ss <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ begin
+ dc_ss <= debug_csr_write_data[0];
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
+ else
+ state <= 3'b001;
+ end
+ case (state)
+ 3'b001:
+ begin
+
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
+ )
+ && (stall_x == 1'b0)
+ )
+ state <= 3'b010;
+ end
+ 3'b010:
+ begin
+
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
+ end
+ 3'b011:
+ begin
+
+
+
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
+
+
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ begin
+ dc_ss <= 1'b0;
+ state <= 3'b100;
+ end
+ end
+ 3'b100:
+ begin
+
+
+
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
+
+
+ state <= 3'b000;
+ end
+ endcase
+ end
+end
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -22946,7 +23032,7 @@ endmodule
-
+
@@ -23083,7 +23169,7 @@ endmodule
-module lm32_instruction_unit_full (
+module lm32_instruction_unit_full_debug (
clk_i,
rst_i,
@@ -23136,11 +23222,12 @@ module lm32_instruction_unit_full (
-
-
-
-
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+
@@ -23176,9 +23263,10 @@ module lm32_instruction_unit_full (
-
-
+ jtag_read_data,
+ jtag_access_complete,
+
@@ -23268,11 +23356,12 @@ input i_rty_i;
-
-
-
-
+input jtag_read_enable;
+input jtag_write_enable;
+input [ 7:0] jtag_write_data;
+input [ (32-1):0] jtag_address;
+
@@ -23313,11 +23402,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
-
-
-wire [ (32-1):0] i_dat_o;
+reg [ (32-1):0] i_dat_o;
+
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -23325,21 +23414,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
-
-
-wire [ (4-1):0] i_sel_o;
+reg [ (4-1):0] i_sel_o;
+
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-wire i_we_o;
+reg i_we_o;
+
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -23351,11 +23440,12 @@ wire [ (2-1):0] i_bte_o;
-
-
-
-
+output [ 7:0] jtag_read_data;
+reg [ 7:0] jtag_read_data;
+output jtag_access_complete;
+wire jtag_access_complete;
+
@@ -23421,8 +23511,9 @@ reg bus_error_f;
-
+reg jtag_access;
+
@@ -23540,7 +23631,7 @@ endfunction
-lm32_icache_full #(
+lm32_icache_full_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -23663,11 +23754,11 @@ assign instruction_f = icache_data_f;
-
-assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
-assign i_sel_o = 4'b1111;
+
+
+
+
assign i_bte_o = 2'b00;
@@ -23784,17 +23875,18 @@ end
-
-
-
-
-
-
-
-
-
-
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+always @(*)
+begin
+ case (jtag_address[1:0])
+ 2'b00: jtag_read_data = i_dat_i[ 31:24];
+ 2'b01: jtag_read_data = i_dat_i[ 23:16];
+ 2'b10: jtag_read_data = i_dat_i[ 15:8];
+ 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ endcase
+end
+
@@ -23819,10 +23911,11 @@ begin
-
-
-
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
+
end
else
@@ -23835,15 +23928,16 @@ begin
if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
-
-
-
-
-
-
-
+ if (jtag_access == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
+ end
+ else
+
begin
if (last_word == 1'b1)
@@ -23876,9 +23970,10 @@ begin
if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
-
+
+
+ i_sel_o <= 4'b1111;
+
i_adr_o <= {first_address, 2'b00};
i_cyc_o <= 1'b1;
@@ -23892,26 +23987,27 @@ begin
end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ else
+ begin
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ begin
+ case (jtag_address[1:0])
+ 2'b00: i_sel_o <= 4'b1000;
+ 2'b01: i_sel_o <= 4'b0100;
+ 2'b10: i_sel_o <= 4'b0010;
+ 2'b11: i_sel_o <= 4'b0001;
+ endcase
+ i_adr_o <= jtag_address;
+ i_dat_o <= {4{jtag_write_data}};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_we_o <= jtag_write_enable;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
+ end
+ end
+
@@ -24251,7 +24347,7 @@ endmodule
-
+
@@ -24386,443 +24482,523 @@ endmodule
-
-
-
+
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module lm32_jtag_full_debug (
-
-
-
-
-
-
+ clk_i,
+ rst_i,
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
+
+ csr,
+ csr_write_enable,
+ csr_write_data,
+ stall_x,
-
-
-
-
+
+
+ jtag_read_data,
+ jtag_access_complete,
-
-
+
+
+ exception_q_w,
-
+
+
+ jtx_csr_read_data,
+ jrx_csr_read_data,
-
-
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
-
-
-
-
-
-
-
+
+
+ jtag_break,
+ jtag_reset,
-
-
-
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d
+ );
-
-
+input clk_i;
+input rst_i;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
+
+input [ (5-1):0] csr;
+input csr_write_enable;
+input [ (32-1):0] csr_write_data;
+input stall_x;
-
-
-
-
+
+
+input [ 7:0] jtag_read_data;
+input jtag_access_complete;
-
-
+
+
+input exception_q_w;
-
-
-
-
-
-
+
+output [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+output jtag_csr_write_enable;
+reg jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;
+wire [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;
+wire [ (5-1):0] jtag_csr;
+output jtag_read_enable;
+reg jtag_read_enable;
+output jtag_write_enable;
+reg jtag_write_enable;
+output [ 7:0] jtag_write_data;
+wire [ 7:0] jtag_write_data;
+output [ (32-1):0] jtag_address;
+wire [ (32-1):0] jtag_address;
-
-
-
-
-
-
-
+
+output jtag_break;
+reg jtag_break;
+output jtag_reset;
+reg jtag_reset;
+
+
+output [ 7:0] jtag_reg_d;
+reg [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
-
-
-
-
+reg rx_update;
+reg rx_update_r;
+reg rx_update_r_r;
+reg rx_update_r_r_r;
-
+wire [ 7:0] rx_byte;
+wire [2:0] rx_addr;
+
+
+reg [ 7:0] uart_tx_byte;
+reg uart_tx_valid;
+reg [ 7:0] uart_rx_byte;
+reg uart_rx_valid;
+
-
-
-
-
-
+reg [ 3:0] command;
+
-
+reg [ 7:0] jtag_byte_0;
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;
-
-
-
-
-
-
-
+reg [ 3:0] state;
+
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
-
-
-
-
-
-
-
+
+
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
+
+
+
+
+assign jtag_reg_addr_d[2] = processing;
-
-
-
-
+
+
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+
-
-
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ rx_update <= 1'b0;
+ rx_update_r <= 1'b0;
+ rx_update_r_r <= 1'b0;
+ rx_update_r_r_r <= 1'b0;
+ end
+ else
+ begin
+ rx_update <= jtag_update;
+ rx_update_r <= rx_update;
+ rx_update_r_r <= rx_update_r;
+ rx_update_r_r_r <= rx_update_r_r;
+ end
+end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'h0;
+ command <= 4'b0000;
+ jtag_reg_d <= 8'h00;
+
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
+
-
+
-
-
-
-
-
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
-
-
+
+
+ uart_tx_byte <= 8'h00;
+ uart_tx_valid <= 1'b0;
+ uart_rx_byte <= 8'h00;
+ uart_rx_valid <= 1'b0;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ end
+ else
+ begin
+
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+ begin
+ case (csr)
+ 5'he:
+ begin
-
-
-
-
-
+ uart_tx_byte <= csr_write_data[ 7:0];
+ uart_tx_valid <= 1'b1;
+ end
+ 5'hf:
+ begin
-
-
-
-
-
+ uart_rx_valid <= 1'b0;
+ end
+ endcase
+ end
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
+ if (exception_q_w == 1'b1)
+ begin
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ case (state)
+ 4'h0:
+ begin
+
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ command <= rx_byte[7:4];
+ case (rx_addr)
+
-
+ 3'b000:
+ begin
+ case (rx_byte[7:4])
+
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 4'h6;
+ end
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 5;
+ end
+ 4'b0101:
+ state <= 4'h1;
+
-
-
+ 4'b0110:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
-
-
-
-
-
-
+ jtag_break <= 1'b1;
+ end
+ 4'b0111:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
+ jtag_reset <= 1'b1;
+ end
+ endcase
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+ 3'b001:
+ begin
+ uart_rx_byte <= rx_byte;
+ uart_rx_valid <= 1'b1;
+ end
+ 3'b010:
+ begin
+ jtag_reg_d <= uart_tx_byte;
+ uart_tx_valid <= 1'b0;
+ end
+
+ default:
+ ;
+ endcase
+ end
+ end
+ 4'h1:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_0 <= rx_byte;
+ state <= 4'h2;
+ end
+ end
+ 4'h2:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_1 <= rx_byte;
+ state <= 4'h3;
+ end
+ end
+ 4'h3:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_2 <= rx_byte;
+ state <= 4'h4;
+ end
+ end
+ 4'h4:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_3 <= rx_byte;
+ if (command == 4'b0001)
+ state <= 4'h6;
+ else
+ state <= 4'h5;
+ end
+ end
+ 4'h5:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_4 <= rx_byte;
+ state <= 4'h6;
+ end
+ end
+ 4'h6:
+ begin
+ case (command)
+ 4'b0001,
+ 4'b0011:
+ begin
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0010,
+ 4'b0100:
+ begin
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0101:
+ begin
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
+ end
+ endcase
+ end
+ 4'h7:
+ begin
+ if (jtag_access_complete == 1'b1)
+ begin
+ jtag_read_enable <= 1'b0;
+ jtag_reg_d <= jtag_read_data;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+ end
+ 4'h8:
+ begin
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+
+ endcase
+ end
+end
+
+endmodule
+
@@ -25040,7 +25216,7 @@ endmodule
-
+
@@ -25177,7 +25353,7 @@ endmodule
-module lm32_interrupt_full (
+module lm32_interrupt_full_debug (
clk_i,
rst_i,
@@ -25186,17 +25362,18 @@ module lm32_interrupt_full (
stall_x,
-
-
-
- exception,
+ non_debug_exception,
+ debug_exception,
+
+
eret_q_x,
-
+ bret_q_x,
+
csr,
csr_write_data,
@@ -25225,20 +25402,21 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
-
-input exception;
+input non_debug_exception;
+input debug_exception;
+
+
input eret_q_x;
-
+input bret_q_x;
+
-input [ (3-1):0] csr;
+input [ (5-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -25259,14 +25437,18 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
reg ie;
reg eie;
-
+reg bie;
+
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -25286,11 +25468,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
@@ -25304,19 +25486,19 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -25327,18 +25509,18 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 5'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -25367,8 +25549,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -25380,13 +25563,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -25394,14 +25585,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -25419,26 +25602,28 @@ always @(posedge clk_i )
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25455,8 +25640,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -25466,13 +25652,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -25480,14 +25674,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -25503,24 +25689,26 @@ always @(posedge clk_i )
end
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25577,12 +25765,6 @@ endmodule
-
-
-
-
-
-
@@ -25608,18 +25790,13 @@ endmodule
-
-
-
-
-
-
-
+
+
+
+
-
-
-
+
@@ -25719,16 +25896,18 @@ endmodule
+
+
-
-
-
+
+
+
@@ -25757,25 +25936,24 @@ endmodule
-
-
-
+
+
-
-
-
+
+
+
@@ -25876,47 +26054,27 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
-
+
-
-
-
-
@@ -25925,8 +26083,6 @@ endmodule
-
-
@@ -25934,19 +26090,28 @@ endmodule
+
+
-
+
+
-
+
+
+
+
+
+
+
+
-
@@ -26007,14 +26172,14 @@ endmodule
+
-
-
-
+
+
@@ -26104,7 +26269,7 @@ endmodule
-module lm32_top_medium_debug (
+module lm32_top_medium (
clk_i,
rst_i,
@@ -26261,225 +26426,221 @@ wire [ (2-1):0] D_BTE_O;
-
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
-wire jtag_update;
-wire [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_q;
-wire jtck;
-wire jrstn;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
-
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
-
-
-
-
-
-
-
-
-lm32_cpu_medium_debug cpu (
-
- .clk_i (clk_i),
-
-
-
-
- .rst_i (rst_i),
-
-
-
- .interrupt (interrupt),
-
-
-
-
-
-
-
-
- .jtag_clk (jtck),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
-
-
-
-
- .I_DAT_I (I_DAT_I),
- .I_ACK_I (I_ACK_I),
- .I_ERR_I (I_ERR_I),
- .I_RTY_I (I_RTY_I),
-
- .D_DAT_I (D_DAT_I),
- .D_ACK_I (D_ACK_I),
- .D_ERR_I (D_ERR_I),
- .D_RTY_I (D_RTY_I),
-
-
-
-
-
-
-
-
-
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d),
-
-
-
-
-
-
-
-
-
-
-
-
- .I_DAT_O (I_DAT_O),
- .I_ADR_O (I_ADR_O),
- .I_CYC_O (I_CYC_O),
- .I_SEL_O (I_SEL_O),
- .I_STB_O (I_STB_O),
- .I_WE_O (I_WE_O),
- .I_CTI_O (I_CTI_O),
- .I_LOCK_O (I_LOCK_O),
- .I_BTE_O (I_BTE_O),
-
-
-
- .D_DAT_O (D_DAT_O),
- .D_ADR_O (D_ADR_O),
- .D_CYC_O (D_CYC_O),
- .D_SEL_O (D_SEL_O),
- .D_STB_O (D_STB_O),
- .D_WE_O (D_WE_O),
- .D_CTI_O (D_CTI_O),
- .D_LOCK_O (D_LOCK_O),
- .D_BTE_O (D_BTE_O)
- );
-
-
-
-
-jtag_cores jtag_cores (
-
- .reg_d (jtag_reg_d),
- .reg_addr_d (jtag_reg_addr_d),
-
- .reg_update (jtag_update),
- .reg_q (jtag_reg_q),
- .reg_addr_q (jtag_reg_addr_q),
- .jtck (jtck),
- .jrstn (jrstn)
- );
+
+
+
+
+
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
+
+
+
+
+
+
+
+
+lm32_cpu_medium cpu (
+
+ .clk_i (clk_i),
+
+
+
+
+ .rst_i (rst_i),
+
+
+
+ .interrupt (interrupt),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ .I_DAT_I (I_DAT_I),
+ .I_ACK_I (I_ACK_I),
+ .I_ERR_I (I_ERR_I),
+ .I_RTY_I (I_RTY_I),
+
+
+
+ .D_DAT_I (D_DAT_I),
+ .D_ACK_I (D_ACK_I),
+ .D_ERR_I (D_ERR_I),
+ .D_RTY_I (D_RTY_I),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ .I_DAT_O (I_DAT_O),
+ .I_ADR_O (I_ADR_O),
+ .I_CYC_O (I_CYC_O),
+ .I_SEL_O (I_SEL_O),
+ .I_STB_O (I_STB_O),
+ .I_WE_O (I_WE_O),
+ .I_CTI_O (I_CTI_O),
+ .I_LOCK_O (I_LOCK_O),
+ .I_BTE_O (I_BTE_O),
+
+
+
+ .D_DAT_O (D_DAT_O),
+ .D_ADR_O (D_ADR_O),
+ .D_CYC_O (D_CYC_O),
+ .D_SEL_O (D_SEL_O),
+ .D_STB_O (D_STB_O),
+ .D_WE_O (D_WE_O),
+ .D_CTI_O (D_CTI_O),
+ .D_LOCK_O (D_LOCK_O),
+ .D_BTE_O (D_BTE_O)
+ );
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -26676,7 +26837,7 @@ endmodule
-
+
@@ -26828,7 +26989,7 @@ endmodule
-module lm32_mc_arithmetic_medium_debug (
+module lm32_mc_arithmetic_medium (
clk_i,
rst_i,
@@ -27347,7 +27508,7 @@ endmodule
-
+
@@ -27484,7 +27645,7 @@ endmodule
-module lm32_cpu_medium_debug (
+module lm32_cpu_medium (
clk_i,
@@ -27505,13 +27666,12 @@ module lm32_cpu_medium_debug (
-
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
+
+
+
+
+
@@ -27540,10 +27700,9 @@ module lm32_cpu_medium_debug (
+
+
- jtag_reg_d,
- jtag_reg_addr_d,
-
@@ -27584,25 +27743,24 @@ module lm32_cpu_medium_debug (
parameter eba_reset = 32'h00000000;
+
-parameter deba_reset = 32'h10000000;
-
+
+
+
+
+
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
-
-
-
-
-
-
+parameter icache_associativity = 1;
+parameter icache_sets = 512;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 0;
+parameter icache_limit = 0;
+
@@ -27622,11 +27780,11 @@ parameter dcache_limit = 0;
+
-parameter watchpoints = 32'h4;
-
-
+parameter watchpoints = 0;
+
@@ -27668,12 +27826,11 @@ input [ (32-1):0] interrupt;
+
+
+
+
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
-
@@ -27713,12 +27870,11 @@ input D_RTY_I;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
-
@@ -27782,9 +27938,8 @@ wire [ (2-1):0] D_BTE_O;
+
-reg valid_a;
-
reg valid_f;
reg valid_d;
@@ -27799,6 +27954,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -27807,8 +27965,8 @@ reg [ 1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [ ((32-2)+2-1):2] branch_predict_address_d;
+wire [ ((32-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -27820,15 +27978,16 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ ((32-2)+2-1):2] branch_offset_d;
+reg [ ((32-2)+2-1):2] branch_target_x;
+reg [ ((32-2)+2-1):2] branch_target_m;
wire [ 0:0] d_result_sel_0_d;
wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+
@@ -27897,15 +28056,14 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
+wire [ (4 -1):0] csr_d;
+reg [ (4 -1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
+
+
-wire break_d;
-reg break_x;
-
wire scall_d;
reg scall_x;
@@ -27918,16 +28076,14 @@ reg eret_m;
-
-wire bret_d;
-reg bret_x;
-wire bret_q_x;
-reg bret_m;
-
+
+
+
+
+
-
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -28079,11 +28235,11 @@ wire [ (32-1):0] cfg2;
reg [ (32-1):0] csr_read_data_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+wire [ ((32-2)+2-1):2] pc_f;
+wire [ ((32-2)+2-1):2] pc_d;
+wire [ ((32-2)+2-1):2] pc_x;
+wire [ ((32-2)+2-1):2] pc_m;
+wire [ ((32-2)+2-1):2] pc_w;
@@ -28097,13 +28253,12 @@ wire [ (32-1):0] instruction_f;
wire [ (32-1):0] instruction_d;
+
+
+
+
+
-wire iflush;
-wire icache_stall_request;
-wire icache_restart_request;
-wire icache_refill_request;
-wire icache_refilling;
-
@@ -28129,32 +28284,25 @@ wire stall_wb_load;
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
+
+
+
-
-wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
-wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
-wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
-wire jtag_access_complete;
-
-
-wire jtag_break;
+
+
+
+
@@ -28184,11 +28332,10 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+reg [ (32-2)+2-1:8] eba;
+
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-
reg [ (3-1):0] eid_x;
@@ -28198,39 +28345,36 @@ reg [ (3-1):0] eid_x;
-
-
-
-wire dc_ss;
+
-wire dc_re;
-wire exception_x;
-reg exception_m;
-wire debug_exception_x;
-reg debug_exception_m;
-reg debug_exception_w;
-wire debug_exception_q_w;
-wire non_debug_exception_x;
-reg non_debug_exception_m;
-reg non_debug_exception_w;
-wire non_debug_exception_q_w;
+
+
+
+
+
+
+
+
+wire exception_x;
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+
-
-
-wire reset_exception;
+
+
-
@@ -28238,10 +28382,9 @@ wire interrupt_exception;
+
+
-wire breakpoint_exception;
-wire watchpoint_exception;
-
@@ -28322,7 +28465,7 @@ endfunction
-lm32_instruction_unit_medium_debug #(
+lm32_instruction_unit_medium #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -28353,9 +28496,8 @@ lm32_instruction_unit_medium_debug #(
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
+
- .iflush (iflush),
-
@@ -28379,12 +28521,11 @@ lm32_instruction_unit_medium_debug #(
+
+
+
+
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
-
@@ -28394,12 +28535,11 @@ lm32_instruction_unit_medium_debug #(
.pc_m (pc_m),
.pc_w (pc_w),
+
+
+
+
- .icache_stall_request (icache_stall_request),
- .icache_restart_request (icache_restart_request),
- .icache_refill_request (icache_refill_request),
- .icache_refilling (icache_refilling),
-
@@ -28420,10 +28560,9 @@ lm32_instruction_unit_medium_debug #(
+
+
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
-
@@ -28438,7 +28577,7 @@ lm32_instruction_unit_medium_debug #(
);
-lm32_decoder_medium_debug decoder (
+lm32_decoder_medium decoder (
.instruction (instruction_d),
@@ -28517,16 +28656,14 @@ lm32_decoder_medium_debug decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
+
- .break_opcode (break_d),
-
.scall (scall_d),
.eret (eret_d),
+
- .bret (bret_d),
-
@@ -28536,7 +28673,7 @@ lm32_decoder_medium_debug decoder (
);
-lm32_load_store_unit_medium_debug #(
+lm32_load_store_unit_medium #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -28702,7 +28839,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium_debug interrupt_unit (
+lm32_interrupt_medium interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -28711,18 +28848,17 @@ lm32_interrupt_medium_debug interrupt_unit (
.stall_x (stall_x),
+
+
- .non_debug_exception (non_debug_exception_q_w),
- .debug_exception (debug_exception_q_w),
-
-
+ .exception (exception_q_w),
+
.eret_q_x (eret_q_x),
+
- .bret_q_x (bret_q_x),
-
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -28737,116 +28873,95 @@ lm32_interrupt_medium_debug interrupt_unit (
-
-lm32_jtag_medium_debug jtag (
+
- .clk_i (clk_i),
- .rst_i (rst_i),
+
+
- .jtag_clk (jtag_clk),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+
+
-
-
- .csr (csr_x),
- .csr_write_data (operand_1_x),
- .csr_write_enable (csr_write_enable_q_x),
- .stall_x (stall_x),
+
+
+
+
-
-
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
+
+
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+
-
-
- .jtx_csr_read_data (jtx_csr_read_data),
- .jrx_csr_read_data (jrx_csr_read_data),
+
+
-
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
+
+
+
+
+
+
+
-
-
- .jtag_break (jtag_break),
- .jtag_reset (reset_exception),
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d)
- );
-
-
+
+
+
-
-lm32_debug_medium_debug #(
- .breakpoints (breakpoints),
- .watchpoints (watchpoints)
- ) hw_debug (
-
- .clk_i (clk_i),
- .rst_i (rst_i),
- .pc_x (pc_x),
- .load_x (load_x),
- .store_x (store_x),
- .load_store_address_x (adder_result_x),
- .csr_write_enable_x (csr_write_enable_q_x),
- .csr_write_data (operand_1_x),
- .csr_x (csr_x),
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- .eret_q_x (eret_q_x),
- .bret_q_x (bret_q_x),
- .stall_x (stall_x),
- .exception_x (exception_x),
- .q_x (q_x),
-
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- .dc_ss (dc_ss),
-
- .dc_re (dc_re),
- .bp_match (bp_match),
- .wp_match (wp_match)
- );
-
@@ -29291,9 +29406,8 @@ assign kill_f = ( (valid_d == 1'b1)
+
- || (icache_refill_request == 1'b1)
-
@@ -29306,9 +29420,8 @@ assign kill_d = (branch_taken_m == 1'b1)
+
- || (icache_refill_request == 1'b1)
-
@@ -29337,25 +29450,21 @@ assign kill_w = 1'b0
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
- )
- && (valid_x == 1'b1)
- )
-
-
- || (jtag_break == 1'b1)
+
+
+
+
+
+
+
+
- ;
-
+
-assign watchpoint_exception = wp_match == 1'b1;
-
@@ -29379,17 +29488,38 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
+
+
+
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
- ;
+
+
+
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
+
+
+
- || (reset_exception == 1'b1)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign exception_x = (system_call_exception == 1'b1)
@@ -29403,9 +29533,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
@@ -29416,54 +29545,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
;
-
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
always @(*)
begin
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+
+
-
+
+
+
+
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
- else
-
@@ -29475,11 +29577,10 @@ begin
+
+
+
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
-
@@ -29491,9 +29592,8 @@ begin
if ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
)
eid_x = 3'h6;
@@ -29529,19 +29629,18 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
+
+
+
+
+
+
+
+
+
+
+
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
- )
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
- )
- && (kill_d == 1'b0)
- )
-
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -29603,14 +29702,16 @@ assign stall_m = (stall_wb_load == 1'b1)
+
+
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
-
-
-
+
+
+ || (I_CYC_O == 1'b1)
+
+
@@ -29643,24 +29744,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
@@ -29671,13 +29769,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
-
+
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
@@ -29692,12 +29790,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
- 1'b1,
-
+ 1'b0,
+
+
@@ -29706,26 +29804,26 @@ assign cfg = {
-
- 1'b1,
-
-
-
- 1'b1,
+ 1'b0,
-
-
+
- 1'b1,
+
+ 1'b0,
+
+
+ 1'b0,
+
+
@@ -29797,22 +29895,19 @@ assign cfg2 = {
+
+
+
+
+
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
-
-
-
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
+
+
+
+
+
- ;
-
@@ -29828,7 +29923,7 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[ (4 -1):0];
always @(*)
@@ -29836,29 +29931,27 @@ begin
case (csr_x)
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 4 'h0,
+ 4 'h1,
+ 4 'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
+ 4 'h6: csr_read_data_x = cfg;
+ 4 'h7: csr_read_data_x = {eba, 8'h00};
+
- 5'h9: csr_read_data_x = {deba, 8'h00};
-
+
+
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
-
- 5'ha: csr_read_data_x = cfg2;
+ 4 'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -29872,40 +29965,36 @@ end
always @(posedge clk_i )
begin
if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ eba <= eba_reset[ (32-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[ (32-2)+2-1:8];
+
+
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
end
end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
- else
- begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
+
+
+
+
+
+
+
+
+
- end
-end
-
@@ -29940,11 +30029,10 @@ end
-
-
+
@@ -29958,20 +30046,19 @@ end
-
-always @(*)
-begin
- if (icache_refill_request == 1'b1)
- valid_a = 1'b0;
- else if (icache_restart_request == 1'b1)
- valid_a = 1'b1;
- else
- valid_a = !icache_refilling;
-end
+
+
+
+
+
+
-
+
+
+
+
@@ -29983,6 +30070,7 @@ end
+
always @(posedge clk_i )
@@ -29999,11 +30087,11 @@ begin
begin
if ((kill_f == 1'b1) || (stall_a == 1'b0))
+
- valid_f <= valid_a;
-
-
+ valid_f <= 1'b1;
+
else if (stall_f == 1'b0)
valid_f <= 1'b0;
@@ -30048,7 +30136,7 @@ begin
operand_0_x <= { 32{1'b0}};
operand_1_x <= { 32{1'b0}};
store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ branch_target_x <= { (32-2){1'b0}};
x_result_sel_csr_x <= 1'b0;
@@ -30085,7 +30173,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
+ csr_x <= { 4 {1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -30108,16 +30196,14 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
+
- break_x <= 1'b0;
-
scall_x <= 1'b0;
eret_x <= 1'b0;
+
- bret_x <= 1'b0;
-
@@ -30126,7 +30212,7 @@ begin
csr_write_enable_x <= 1'b0;
operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ branch_target_m <= { (32-2){1'b0}};
m_result_sel_compare_m <= 1'b0;
@@ -30159,10 +30245,9 @@ begin
+
+
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
-
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -30174,13 +30259,13 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
-
+
+ exception_w <= 1'b0;
+
+
@@ -30199,7 +30284,7 @@ begin
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
@@ -30258,9 +30343,8 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
+
- break_x <= break_d;
-
scall_x <= scall_d;
@@ -30269,9 +30353,8 @@ begin
eret_x <= eret_d;
+
- bret_x <= bret_d;
-
write_enable_x <= write_enable_d;
end
@@ -30323,40 +30406,40 @@ begin
-
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
- else
- write_idx_m <= write_idx_x;
-
-
+
+
+
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else
+ write_idx_m <= write_idx_x;
+
+
condition_met_m <= condition_met_x;
+
+
+
+
+
+
+
+
+
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
- branch_target_m <= {deba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= {eba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= branch_target_x;
-
-
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+
@@ -30368,16 +30451,14 @@ begin
eret_m <= eret_q_x;
+
- bret_m <= bret_q_x;
-
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
+
- debug_exception_m <= debug_exception_x;
- non_debug_exception_m <= non_debug_exception_x;
-
end
@@ -30423,13 +30504,13 @@ begin
write_enable_w <= write_enable_m;
-
- debug_exception_w <= debug_exception_m;
- non_debug_exception_w <= non_debug_exception_m;
-
+
+ exception_w <= exception_m;
+
+
@@ -30836,7 +30917,7 @@ endmodule
-
+
@@ -30973,7 +31054,7 @@ endmodule
-module lm32_load_store_unit_medium_debug (
+module lm32_load_store_unit_medium (
clk_i,
rst_i,
@@ -32050,7 +32131,7 @@ endmodule
-
+
@@ -32285,7 +32366,7 @@ endmodule
-module lm32_decoder_medium_debug (
+module lm32_decoder_medium (
instruction,
@@ -32364,16 +32445,14 @@ module lm32_decoder_medium_debug (
bi_conditional,
bi_unconditional,
+
- break_opcode,
-
scall,
eret,
+
- bret,
-
@@ -32457,8 +32536,8 @@ output [ (5-1):0] write_idx;
wire [ (5-1):0] write_idx;
output [ (32-1):0] immediate;
wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [ ((32-2)+2-1):2] branch_offset;
+wire [ ((32-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
@@ -32507,20 +32586,18 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-output break_opcode;
-wire break_opcode;
+
+
output scall;
wire scall;
output eret;
wire eret;
-
-output bret;
-wire bret;
+
+
@@ -32542,6 +32619,90 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -32697,9 +32858,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -32874,16 +33034,14 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
+
-assign break_opcode = op_raise & ~instruction[2];
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
+
-assign bret = op_b & (instruction[25:21] == 5'd31);
-
@@ -33137,7 +33295,7 @@ endmodule
-
+
@@ -33272,499 +33430,426 @@ endmodule
+
+
+
+
+
+
+
+
+
-
+
+
+
+
-
+
+
+
+
+
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-module lm32_icache_medium_debug (
+
+
+
- clk_i,
- rst_i,
- stall_a,
- stall_f,
- address_a,
- address_f,
- read_enable_f,
- refill_ready,
- refill_data,
- iflush,
-
+
+
+
+
+
+
+
- valid_d,
- branch_predict_taken_d,
-
- stall_request,
- restart_request,
- refill_request,
- refill_address,
- refilling,
- inst
- );
+
+
+
+
+
+
+
+
+
+
+
+
-parameter associativity = 1;
-parameter sets = 512;
-parameter bytes_per_line = 16;
-parameter base_address = 0;
-parameter limit = 0;
+
+
+
+
-localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
-localparam addr_set_width = clogb2(sets)-1;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-localparam addr_set_lsb = (addr_offset_msb+1);
-localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
-localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
-localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
-input clk_i;
-input rst_i;
-input stall_a;
-input stall_f;
+
-input valid_d;
-input branch_predict_taken_d;
-
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
-input read_enable_f;
-input refill_ready;
-input [ (32-1):0] refill_data;
-input iflush;
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-output stall_request;
-wire stall_request;
-output restart_request;
-reg restart_request;
-output refill_request;
-wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-output refilling;
-reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
-wire enable;
-wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
-wire [0:associativity-1] way_valid;
-wire [0:associativity-1] way_match;
-wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+
+
+
-reg [ 3:0] state;
-wire flushing;
-wire check;
-wire refill;
-reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
-wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
-genvar i;
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
-
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- generate
- for (i = 0; i < associativity; i = i + 1)
- begin : memories
-
- lm32_ram
- #(
+
+
+
+
+
- .data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
-
-)
- way_0_data_ram
- (
-
- .read_clk (clk_i),
- .write_clk (clk_i),
- .reset (rst_i),
- .read_address (dmem_read_address),
- .enable_read (enable),
- .write_address (dmem_write_address),
- .enable_write ( 1'b1),
- .write_enable (way_mem_we[i]),
- .write_data (refill_data),
+
- .read_data (way_data[i])
- );
-
- lm32_ram
- #(
-
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
- )
- way_0_tag_ram
- (
-
- .read_clk (clk_i),
- .write_clk (clk_i),
- .reset (rst_i),
- .read_address (tmem_read_address),
- .enable_read (enable),
- .write_address (tmem_write_address),
- .enable_write ( 1'b1),
- .write_enable (way_mem_we[i] | flushing),
- .write_data (tmem_write_data),
-
- .read_data ({way_tag[i], way_valid[i]})
- );
+
- end
-endgenerate
-
-
-
-
-
-
-generate
- for (i = 0; i < associativity; i = i + 1)
- begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
- end
-endgenerate
-
-
-generate
- if (associativity == 1)
- begin : inst_1
-assign inst = way_match[0] ? way_data[0] : 32'b0;
- end
- else if (associativity == 2)
- begin : inst_2
-assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
- end
-endgenerate
-
-
-generate
- if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
- else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
-endgenerate
-
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
-
-
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
-assign tmem_write_address = flushing
- ? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
-
-
-generate
- if (bytes_per_line > 4)
-assign last_refill = refill_offset == {addr_offset_width{1'b1}};
- else
-assign last_refill = 1'b1;
-endgenerate
-
-
-assign enable = (stall_a == 1'b0);
-
-
-generate
- if (associativity == 1)
- begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
- end
- else
- begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
- end
-endgenerate
-
-
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
-
-
-assign flushing = |state[1:0];
-assign check = state[2];
-assign refill = state[3];
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-generate
- if (associativity >= 2)
- begin : way_select
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
- else
- begin
- if (miss == 1'b1)
- refill_way_select <= {refill_way_select[0], refill_way_select[1]};
- end
-end
- end
-endgenerate
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
- else
- refilling <= refill;
-end
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
- end
- else
- begin
- case (state)
-
+
+
+
+
+
- 4'b0001:
- begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
- flush_set <= flush_set - 1'b1;
- end
-
- 4'b0010:
- begin
- if (flush_set == { addr_set_width{1'b0}})
-
-
+
+
+
-
-
+
+
+
- state <= 4'b0100;
-
- flush_set <= flush_set - 1'b1;
- end
- 4'b0100:
- begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
- begin
- refill_address <= address_f;
- state <= 4'b0010;
- end
- else if (miss == 1'b1)
- begin
- refill_address <= address_f;
- state <= 4'b1000;
- end
- end
-
+
+
+
- 4'b1000:
- begin
- if (refill_ready == 1'b1)
- begin
- if (last_refill == 1'b1)
- begin
- restart_request <= 1'b1;
- state <= 4'b0100;
- end
- end
- end
- endcase
- end
-end
+
+
-generate
- if (bytes_per_line > 4)
- begin
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- else
- begin
- case (state)
-
-
- 4'b0100:
- begin
- if (iflush == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- end
+
-
- 4'b1000:
- begin
- if (refill_ready == 1'b1)
- refill_offset <= refill_offset + 1'b1;
- end
- endcase
- end
-end
- end
-endgenerate
-
-endmodule
-
@@ -33985,7 +34070,7 @@ endmodule
-
+
@@ -34812,7 +34897,7 @@ endmodule
-
+
@@ -34948,165 +35033,127 @@ endmodule
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-module lm32_debug_medium_debug (
- clk_i,
- rst_i,
- pc_x,
- load_x,
- store_x,
- load_store_address_x,
- csr_write_enable_x,
- csr_write_data,
- csr_x,
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
+
+
+
+
+
+
+
+
+
-
-
-
- eret_q_x,
- bret_q_x,
- stall_x,
- exception_x,
- q_x,
-
-
+
+
-
-
-
- dc_ss,
+
+
+
+
-
- dc_re,
- bp_match,
- wp_match
- );
+
+
+
+
+
+
+
+
-parameter breakpoints = 0;
-parameter watchpoints = 0;
+
+
-input clk_i;
-input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-input load_x;
-input store_x;
-input [ (32-1):0] load_store_address_x;
-input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
-
-
+
+
-input eret_q_x;
-input bret_q_x;
-input stall_x;
-input exception_x;
-input q_x;
-
+
+
+
+
+
+
+
+
-
+
+
-
-
-
-
-
-
-
-
-output dc_ss;
-reg dc_ss;
+
+
+
+
+
+
-output dc_re;
-reg dc_re;
-output bp_match;
-wire bp_match;
-output wp_match;
-wire wp_match;
-
-
-
-
-
-genvar i;
-
-
-
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
-reg bp_e[0:breakpoints-1];
-wire [0:breakpoints-1]bp_match_n;
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
-wire [0:watchpoints]wp_match_n;
-wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
-
-reg [ 2:0] state;
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
@@ -35114,6 +35161,7 @@ reg [ 2:0] state;
+
@@ -35121,35 +35169,48 @@ reg [ 2:0] state;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
+
+
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
+
+
+
+
+
+
@@ -35158,191 +35219,132 @@ endfunction
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
- end
-endgenerate
-generate
-
+
+
+
- if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
- else
-assign bp_match = state == 3'b011;
-
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-endgenerate
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_comb
-assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
- end
-endgenerate
-generate
- if (watchpoints > 0)
-assign wp_match = |wp_match_n;
- else
-assign wp_match = 1'b0;
-endgenerate
-
-
-
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
- begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
- bp_e[i] <= debug_csr_write_data[0];
- end
- end
-end
- end
-endgenerate
-
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
- end
- else
- begin
- if (debug_csr_write_enable == 1'b1)
- begin
- if (debug_csr == 5'h8)
- wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
- wp[i] <= debug_csr_write_data;
- end
- end
-end
- end
-endgenerate
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- dc_re <= debug_csr_write_data[1];
- end
-end
-
-
-
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 3'b000;
- dc_ss <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- begin
- dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
- else
- state <= 3'b001;
- end
- case (state)
- 3'b001:
- begin
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
- )
- && (stall_x == 1'b0)
- )
- state <= 3'b010;
- end
- 3'b010:
- begin
+
+
+
+
+
+
+
+
+
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
- end
- 3'b011:
- begin
+
+
+
+
+
-
+
-
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- begin
- dc_ss <= 1'b0;
- state <= 3'b100;
- end
- end
- 3'b100:
- begin
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- state <= 3'b000;
- end
- endcase
- end
-end
-
-endmodule
-
@@ -35578,7 +35580,7 @@ endmodule
-
+
@@ -35715,7 +35717,7 @@ endmodule
-module lm32_instruction_unit_medium_debug (
+module lm32_instruction_unit_medium (
clk_i,
rst_i,
@@ -35740,9 +35742,8 @@ module lm32_instruction_unit_medium_debug (
branch_mispredict_taken_m,
branch_target_m,
+
- iflush,
-
@@ -35766,12 +35767,11 @@ module lm32_instruction_unit_medium_debug (
+
+
+
+
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
-
@@ -35781,12 +35781,11 @@ module lm32_instruction_unit_medium_debug (
pc_m,
pc_w,
+
+
+
+
- icache_stall_request,
- icache_restart_request,
- icache_refill_request,
- icache_refilling,
-
@@ -35807,10 +35806,9 @@ module lm32_instruction_unit_medium_debug (
+
+
- jtag_read_data,
- jtag_access_complete,
-
@@ -35856,7 +35854,7 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [ ((32-2)+2-1):2] branch_predict_address_d;
@@ -35866,12 +35864,11 @@ input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+input [ ((32-2)+2-1):2] branch_target_m;
+
-input iflush;
-
@@ -35897,40 +35894,38 @@ input i_rty_i;
+
+
+
+
-input jtag_read_enable;
-input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+output [ ((32-2)+2-1):2] pc_f;
+reg [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;
+reg [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;
+reg [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;
+reg [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;
+reg [ ((32-2)+2-1):2] pc_w;
+
+
+
+
+
+
+
+
-output icache_stall_request;
-wire icache_stall_request;
-output icache_restart_request;
-wire icache_restart_request;
-output icache_refill_request;
-wire icache_refill_request;
-output icache_refilling;
-wire icache_refilling;
-
@@ -35943,11 +35938,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
+
-reg [ (32-1):0] i_dat_o;
-
-
+wire [ (32-1):0] i_dat_o;
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -35955,21 +35950,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
+
-reg [ (4-1):0] i_sel_o;
-
-
+wire [ (4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
+
-reg i_we_o;
-
-
+wire i_we_o;
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -35981,12 +35976,11 @@ wire [ (2-1):0] i_bte_o;
+
+
+
+
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
-output jtag_access_complete;
-wire jtag_access_complete;
-
@@ -36007,30 +36001,31 @@ reg [ (32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [ ((32-2)+2-1):2] pc_a;
+
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
+
+
+
+
+
+
+
+
+
-wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
-reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
-wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
-
-
+
+
+reg [ (32-1):0] wb_data_f;
+
+
@@ -36050,9 +36045,8 @@ wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-reg jtag_access;
-
@@ -36169,57 +36163,53 @@ endfunction
-
-lm32_icache_medium_debug #(
- .associativity (associativity),
- .sets (sets),
- .bytes_per_line (bytes_per_line),
- .base_address (base_address),
- .limit (limit)
- ) icache (
+
+
+
+
+
+
+
- .clk_i (clk_i),
- .rst_i (rst_i),
- .stall_a (stall_a),
- .stall_f (stall_f),
- .branch_predict_taken_d (branch_predict_taken_d),
- .valid_d (valid_d),
- .address_a (pc_a),
- .address_f (pc_f),
- .read_enable_f (icache_read_enable_f),
- .refill_ready (icache_refill_ready),
- .refill_data (icache_refill_data),
- .iflush (iflush),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- .stall_request (icache_stall_request),
- .restart_request (icache_restart_request),
- .refill_request (icache_refill_request),
- .refill_address (icache_refill_address),
- .refilling (icache_refilling),
- .inst (icache_data_f)
- );
-
-
-
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+
+
+
+
-
+
-
- ;
-
+
+
@@ -36247,11 +36237,10 @@ begin
pc_a = branch_predict_address_d;
else
+
+
+
- if (icache_restart_request == 1'b1)
- pc_a = restart_address;
- else
-
pc_a = pc_f + 1'b1;
end
@@ -36264,25 +36253,25 @@ end
-
-
+
+
-assign instruction_f = icache_data_f;
-
-
-
+
+
-
+assign instruction_f = wb_data_f;
+
+
@@ -36290,11 +36279,11 @@ assign instruction_f = icache_data_f;
-
-
-
-
+assign i_dat_o = 32'd0;
+assign i_we_o = 1'b0;
+assign i_sel_o = 4'b1111;
+
assign i_bte_o = 2'b00;
@@ -36303,32 +36292,31 @@ assign i_bte_o = 2'b00;
-generate
- case (bytes_per_line)
- 4:
- begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = icache_refill_address;
- end
- 8:
- begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
-assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
- end
- 16:
- begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
-assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
- end
- endcase
-endgenerate
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -36341,10 +36329,10 @@ begin
if (rst_i == 1'b1)
begin
pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_d <= { (32-2){1'b0}};
+ pc_x <= { (32-2){1'b0}};
+ pc_m <= { (32-2){1'b0}};
+ pc_w <= { (32-2){1'b0}};
end
else
begin
@@ -36362,14 +36350,13 @@ end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- else
- begin
-
+
+
+
+
+
@@ -36381,18 +36368,14 @@ begin
+
+
+
-
-
- if (icache_refill_request == 1'b1)
- restart_address <= icache_refill_address;
-
-
+
+
- end
-end
-
@@ -36411,152 +36394,23 @@ end
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
-always @(*)
-begin
- case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
- endcase
-end
-
-
-
-
-
-
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
-
-
-
-
-
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
-
-
- end
- else
- begin
- icache_refill_ready <= 1'b0;
-
- if (i_cyc_o == 1'b1)
- begin
-
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
- begin
-
-
- if (jtag_access == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
- end
- else
+
- begin
- if (last_word == 1'b1)
- begin
-
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
- end
-
- i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
- i_cti_o <= next_cycle_type;
-
- icache_refill_ready <= 1'b1;
- icache_refill_data <= i_dat_i;
- end
- end
-
-
-
-
-
-
-
-
- end
- else
- begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
- begin
-
-
- i_sel_o <= 4'b1111;
-
+
+
+
+
+
- i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_cti_o <= first_cycle_type;
-
-
-
- end
-
- else
- begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
- begin
- case (jtag_address[1:0])
- 2'b00: i_sel_o <= 4'b1000;
- 2'b01: i_sel_o <= 4'b0100;
- 2'b10: i_sel_o <= 4'b0010;
- 2'b11: i_sel_o <= 4'b0001;
- endcase
- i_adr_o <= jtag_address;
- i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
- end
- end
-
-
-
-
-
-
-
-
-
-
- end
- end
-end
-
+
@@ -36567,23 +36421,50 @@ end
+
+
+
+
+
+
+
-
+
+
+
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
@@ -36595,12 +36476,7 @@ end
-
-
-
-
-
@@ -36608,45 +36484,146 @@ end
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- instruction_d <= { 32{1'b0}};
-
-
-
-
- end
- else
- begin
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= { 32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ wb_data_f <= { 32{1'b0}};
+
+
+
+
+ end
+ else
+ begin
+
+ if (i_cyc_o == 1'b1)
+ begin
+
+ if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ begin
+
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+
+ wb_data_f <= i_dat_i;
+ end
+
+
+
+
+
+
+
+
+ end
+ else
+ begin
+
+ if ( (stall_a == 1'b0)
+
+
+
+
+ )
+ begin
+
+
+
+
+
+ i_adr_o <= {pc_a, 2'b00};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+
+
+
+
+ end
+ else
+ begin
+ if ( (stall_a == 1'b0)
+
+
+
+
+ )
+ begin
+
+
+
+
+ end
+ end
+ end
+ end
+end
+
+
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ instruction_d <= { 32{1'b0}};
+
+
+
+
+ end
+ else
+ begin
if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
@@ -36875,7 +36852,7 @@ endmodule
-
+
@@ -37010,523 +36987,443 @@ endmodule
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-module lm32_jtag_medium_debug (
- clk_i,
- rst_i,
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
-
- csr,
- csr_write_enable,
- csr_write_data,
- stall_x,
+
+
+
+
+
+
+
+
+
+
-
-
- jtag_read_data,
- jtag_access_complete,
+
+
-
-
- exception_q_w,
-
-
- jtx_csr_read_data,
- jrx_csr_read_data,
+
+
+
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
+
+
+
+
+
+
+
-
-
- jtag_break,
- jtag_reset,
+
+
- jtag_reg_d,
- jtag_reg_addr_d
- );
-
+
+
+
-input clk_i;
-input rst_i;
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
+
+
-
+
+
+
+
-input [ (5-1):0] csr;
-input csr_write_enable;
-input [ (32-1):0] csr_write_data;
-input stall_x;
+
+
+
+
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+
+
-
-
-input exception_q_w;
+
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
-
-
-output jtag_csr_write_enable;
-reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
-output jtag_read_enable;
-reg jtag_read_enable;
-output jtag_write_enable;
-reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-output jtag_break;
-reg jtag_break;
-output jtag_reset;
-reg jtag_reset;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
+
+
+
+
-reg rx_update;
-reg rx_update_r;
-reg rx_update_r_r;
-reg rx_update_r_r_r;
-
+
+
+
+
-wire [ 7:0] rx_byte;
-wire [2:0] rx_addr;
+
-
-reg [ 7:0] uart_tx_byte;
-reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
-reg uart_rx_valid;
-
+
+
+
+
+
-reg [ 3:0] command;
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+
+
+
+
+
+
+
-reg [ 3:0] state;
-
+
-
-assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
-assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_write_data = jtag_byte_4;
+
+
+
+
-
-
-assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
+
+
-
+
-assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+
+
-assign rx_byte = jtag_reg_q;
-assign rx_addr = jtag_reg_addr_q;
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- rx_update <= 1'b0;
- rx_update_r <= 1'b0;
- rx_update_r_r <= 1'b0;
- rx_update_r_r_r <= 1'b0;
- end
- else
- begin
- rx_update <= jtag_update;
- rx_update_r <= rx_update;
- rx_update_r_r <= rx_update_r;
- rx_update_r_r_r <= rx_update_r_r;
- end
-end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'h0;
- command <= 4'b0000;
- jtag_reg_d <= 8'h00;
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
-
-
+
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+
+
+
+
+
+
+
+
+
-
-
- uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
- uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
+
+
- end
- else
- begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
- begin
- case (csr)
- 5'he:
- begin
-
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
- end
- 5'hf:
- begin
-
- uart_rx_valid <= 1'b0;
- end
- endcase
- end
-
-
-
+
+
+
+
+
+
+
+
+
+
- if (exception_q_w == 1'b1)
- begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
- end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- case (state)
- 4'h0:
- begin
+
+
+
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- command <= rx_byte[7:4];
- case (rx_addr)
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 3'b000:
- begin
- case (rx_byte[7:4])
-
+
+
+
+
+
+
+
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
- end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 5;
- end
- 4'b0101:
- state <= 4'h1;
-
+
- 4'b0110:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
- jtag_break <= 1'b1;
- end
- 4'b0111:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
+
+
+
+
+
+
+
+
+
- jtag_reset <= 1'b1;
- end
- endcase
- end
+
+
+
+
+
-
-
+
+
- 3'b001:
- begin
- uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
- end
- 3'b010:
- begin
- jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
- end
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- default:
- ;
- endcase
- end
- end
- 4'h1:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_0 <= rx_byte;
- state <= 4'h2;
- end
- end
- 4'h2:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_1 <= rx_byte;
- state <= 4'h3;
- end
- end
- 4'h3:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_2 <= rx_byte;
- state <= 4'h4;
- end
- end
- 4'h4:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
- else
- state <= 4'h5;
- end
- end
- 4'h5:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_4 <= rx_byte;
- state <= 4'h6;
- end
- end
- 4'h6:
- begin
- case (command)
- 4'b0001,
- 4'b0011:
- begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0010,
- 4'b0100:
- begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0101:
- begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
- end
- endcase
- end
- 4'h7:
- begin
- if (jtag_access_complete == 1'b1)
- begin
- jtag_read_enable <= 1'b0;
- jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
- end
- 4'h8:
- begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
-
- endcase
- end
-end
-
-endmodule
-
@@ -37744,7 +37641,7 @@ endmodule
-
+
@@ -37881,7 +37778,7 @@ endmodule
-module lm32_interrupt_medium_debug (
+module lm32_interrupt_medium (
clk_i,
rst_i,
@@ -37890,18 +37787,17 @@ module lm32_interrupt_medium_debug (
stall_x,
-
- non_debug_exception,
- debug_exception,
-
+
+
+ exception,
+
eret_q_x,
+
- bret_q_x,
-
csr,
csr_write_data,
@@ -37930,21 +37826,20 @@ input [interrupts-1:0] interrupt;
input stall_x;
+
+
-input non_debug_exception;
-input debug_exception;
-
-
+input exception;
+
input eret_q_x;
+
-input bret_q_x;
-
-input [ (5-1):0] csr;
+input [ (4 -1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -37965,15 +37860,17 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
reg ie;
reg eie;
+
-reg bie;
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -37993,11 +37890,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
- bie,
-
+
+ 1'b0,
+
eie,
ie
@@ -38011,19 +37908,19 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
+ 4 'h2: csr_read_data = ip;
+ 4 'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -38034,18 +37931,18 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
+ 4 'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -38074,9 +37971,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -38088,21 +37984,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -38110,6 +37998,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -38127,28 +38023,26 @@ always @(posedge clk_i )
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h1)
+ if (csr == 4 'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -38165,9 +38059,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -38177,21 +38070,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -38199,6 +38084,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -38214,26 +38107,24 @@ always @(posedge clk_i )
end
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -38599,7 +38490,7 @@ endmodule
-
+
@@ -38817,7 +38708,7 @@ endmodule
-module lm32_top_medium_icache_debug (
+module lm32_top_medium_debug (
clk_i,
rst_i,
@@ -39061,7 +38952,7 @@ endfunction
-lm32_cpu_medium_icache_debug cpu (
+lm32_cpu_medium_debug cpu (
.clk_i (clk_i),
@@ -39389,7 +39280,7 @@ endmodule
-
+
@@ -39541,7 +39432,7 @@ endmodule
-module lm32_mc_arithmetic_medium_icache_debug (
+module lm32_mc_arithmetic_medium_debug (
clk_i,
rst_i,
@@ -40060,7 +39951,7 @@ endmodule
-
+
@@ -40197,7 +40088,7 @@ endmodule
-module lm32_cpu_medium_icache_debug (
+module lm32_cpu_medium_debug (
clk_i,
@@ -40512,6 +40403,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -40542,6 +40436,7 @@ wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+
@@ -40918,6 +40813,8 @@ wire dc_ss;
wire dc_re;
+wire bp_match;
+wire wp_match;
wire exception_x;
reg exception_m;
wire debug_exception_x;
@@ -41035,7 +40932,7 @@ endfunction
-lm32_instruction_unit_medium_icache_debug #(
+lm32_instruction_unit_medium_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -41151,7 +41048,7 @@ lm32_instruction_unit_medium_icache_debug #(
);
-lm32_decoder_medium_icache_debug decoder (
+lm32_decoder_medium_debug decoder (
.instruction (instruction_d),
@@ -41249,7 +41146,7 @@ lm32_decoder_medium_icache_debug decoder (
);
-lm32_load_store_unit_medium_icache_debug #(
+lm32_load_store_unit_medium_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -41415,7 +41312,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium_icache_debug interrupt_unit (
+lm32_interrupt_medium_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -41451,7 +41348,7 @@ lm32_interrupt_medium_icache_debug interrupt_unit (
-lm32_jtag_medium_icache_debug jtag (
+lm32_jtag_medium_debug jtag (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -41515,7 +41412,7 @@ lm32_jtag_medium_icache_debug jtag (
-lm32_debug_medium_icache_debug #(
+lm32_debug_medium_debug #(
.breakpoints (breakpoints),
.watchpoints (watchpoints)
) hw_debug (
@@ -43549,7 +43446,7 @@ endmodule
-
+
@@ -43686,7 +43583,7 @@ endmodule
-module lm32_load_store_unit_medium_icache_debug (
+module lm32_load_store_unit_medium_debug (
clk_i,
rst_i,
@@ -44763,7 +44660,7 @@ endmodule
-
+
@@ -44998,7 +44895,7 @@ endmodule
-module lm32_decoder_medium_icache_debug (
+module lm32_decoder_medium_debug (
instruction,
@@ -45255,6 +45152,90 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -45410,9 +45391,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -45850,7 +45830,7 @@ endmodule
-
+
@@ -46028,7 +46008,7 @@ endmodule
-module lm32_icache_medium_icache_debug (
+module lm32_icache_medium_debug (
clk_i,
rst_i,
@@ -46698,7 +46678,7 @@ endmodule
-
+
@@ -47525,7 +47505,7 @@ endmodule
-
+
@@ -47679,7 +47659,7 @@ endmodule
-module lm32_debug_medium_icache_debug (
+module lm32_debug_medium_debug (
clk_i,
rst_i,
@@ -48291,7 +48271,7 @@ endmodule
-
+
@@ -48428,7 +48408,7 @@ endmodule
-module lm32_instruction_unit_medium_icache_debug (
+module lm32_instruction_unit_medium_debug (
clk_i,
rst_i,
@@ -48883,7 +48863,7 @@ endfunction
-lm32_icache_medium_icache_debug #(
+lm32_icache_medium_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -49588,7 +49568,7 @@ endmodule
-
+
@@ -49775,7 +49755,7 @@ endmodule
-module lm32_jtag_medium_icache_debug (
+module lm32_jtag_medium_debug (
clk_i,
rst_i,
@@ -50457,7 +50437,7 @@ endmodule
-
+
@@ -50594,7 +50574,7 @@ endmodule
-module lm32_interrupt_medium_icache_debug (
+module lm32_interrupt_medium_debug (
clk_i,
rst_i,
@@ -50678,6 +50658,9 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
@@ -52075,7 +52058,7 @@ endmodule
-
+
@@ -52746,7 +52729,7 @@ endmodule
-
+
@@ -53193,6 +53176,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -53223,6 +53209,7 @@ wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+
@@ -53291,8 +53278,8 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (4 -1):0] csr_d;
+reg [ (4 -1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
@@ -53585,6 +53572,8 @@ reg [ (3-1):0] eid_x;
+
+
@@ -55133,7 +55122,7 @@ assign cfg2 = {
assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 3'h3)
+ && (csr_d == 4 'h3)
&& (stall_d == 1'b0)
&& (kill_d == 1'b0)
&& (valid_d == 1'b1))
@@ -55161,7 +55150,7 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (4 -1):0];
always @(*)
@@ -55169,17 +55158,17 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 4 'h0,
+ 4 'h1,
+ 4 'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 4 'h6: csr_read_data_x = cfg;
+ 4 'h7: csr_read_data_x = {eba, 8'h00};
@@ -55189,7 +55178,7 @@ begin
- 3'ha: csr_read_data_x = cfg2;
+ 4 'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -55206,7 +55195,7 @@ begin
eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
@@ -55412,7 +55401,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 4 {1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -56156,7 +56145,7 @@ endmodule
-
+
@@ -57370,7 +57359,7 @@ endmodule
-
+
@@ -57858,6 +57847,90 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -58013,9 +58086,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -58451,7 +58523,7 @@ endmodule
-
+
@@ -59299,7 +59371,7 @@ endmodule
-
+
@@ -60126,7 +60198,7 @@ endmodule
-
+
@@ -60809,7 +60881,7 @@ endmodule
-
+
@@ -62096,7 +62168,7 @@ endmodule
-
+
@@ -62885,7 +62957,7 @@ endmodule
-
+
@@ -63083,7 +63155,7 @@ input eret_q_x;
-input [ (3-1):0] csr;
+input [ (4 -1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -63104,6 +63176,9 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
@@ -63149,7 +63224,7 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
@@ -63160,8 +63235,8 @@ begin
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 4 'h2: csr_read_data = ip;
+ 4 'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -63172,7 +63247,7 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
@@ -63183,7 +63258,7 @@ begin
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 4 'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -63272,7 +63347,7 @@ always @(posedge clk_i )
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
@@ -63281,9 +63356,9 @@ always @(posedge clk_i )
end
- if (csr == 3'h1)
+ if (csr == 4 'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -63356,7 +63431,7 @@ always @(posedge clk_i )
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
@@ -63365,7 +63440,7 @@ always @(posedge clk_i )
end
- if (csr == 3'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -63422,6 +63497,10 @@ endmodule
+
+
+
+
@@ -63447,13 +63526,20 @@ endmodule
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
+
+
@@ -63553,18 +63639,16 @@ endmodule
-
-
-
-
+
+
+
-
@@ -63593,24 +63677,25 @@ endmodule
-
+
+
+
-
-
+
+
+
-
-
@@ -63711,24 +63796,34 @@ endmodule
-
-
+
+
+
+
+
+
+
+
+
+
-
+
-
+
+
+
@@ -63740,6 +63835,8 @@ endmodule
+
+
@@ -63747,28 +63844,29 @@ endmodule
-
-
+
-
-
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
+
@@ -63829,14 +63927,14 @@ endmodule
-
-
+
+
+
-
@@ -63926,7 +64024,7 @@ endmodule
-module lm32_top_medium (
+module lm32_top_medium_icache_debug (
clk_i,
rst_i,
@@ -64083,14 +64181,15 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
-
-
-
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+
@@ -64169,7 +64268,7 @@ endfunction
-lm32_cpu_medium cpu (
+lm32_cpu_medium_icache_debug cpu (
.clk_i (clk_i),
@@ -64190,12 +64289,13 @@ lm32_cpu_medium cpu (
-
-
-
-
-
+
+ .jtag_clk (jtck),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
@@ -64224,9 +64324,10 @@ lm32_cpu_medium cpu (
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d),
+
@@ -64261,20 +64362,21 @@ lm32_cpu_medium cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
+
+jtag_cores jtag_cores (
-
-
-
-
-
-
-
-
+ .reg_d (jtag_reg_d),
+ .reg_addr_d (jtag_reg_addr_d),
-
+ .reg_update (jtag_update),
+ .reg_q (jtag_reg_q),
+ .reg_addr_q (jtag_reg_addr_q),
+ .jtck (jtck),
+ .jrstn (jrstn)
+ );
+
endmodule
@@ -64494,7 +64596,7 @@ endmodule
-
+
@@ -64646,7 +64748,7 @@ endmodule
-module lm32_mc_arithmetic_medium (
+module lm32_mc_arithmetic_medium_icache_debug (
clk_i,
rst_i,
@@ -65165,7 +65267,7 @@ endmodule
-
+
@@ -65302,7 +65404,7 @@ endmodule
-module lm32_cpu_medium (
+module lm32_cpu_medium_icache_debug (
clk_i,
@@ -65323,12 +65425,13 @@ module lm32_cpu_medium (
-
-
-
-
-
+
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
@@ -65357,9 +65460,10 @@ module lm32_cpu_medium (
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d,
+
@@ -65400,24 +65504,25 @@ module lm32_cpu_medium (
parameter eba_reset = 32'h00000000;
-
+parameter deba_reset = 32'h10000000;
+
-
-
-
-
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 512;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 0;
-parameter icache_limit = 0;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
+
+
+
+
+
@@ -65437,11 +65542,11 @@ parameter dcache_limit = 0;
-
-
-parameter watchpoints = 0;
+parameter watchpoints = 32'h4;
+
+
@@ -65483,11 +65588,12 @@ input [ (32-1):0] interrupt;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
@@ -65527,11 +65633,12 @@ input D_RTY_I;
-
-
-
-
+output [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
@@ -65595,8 +65702,9 @@ wire [ (2-1):0] D_BTE_O;
-
+reg valid_a;
+
reg valid_f;
reg valid_d;
@@ -65611,6 +65719,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -65619,8 +65730,8 @@ reg [ 1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((32-2)+2-1):2] branch_predict_address_d;
-wire [ ((32-2)+2-1):2] branch_target_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -65632,15 +65743,16 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((32-2)+2-1):2] branch_offset_d;
-reg [ ((32-2)+2-1):2] branch_target_x;
-reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
wire [ 0:0] d_result_sel_0_d;
wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+
@@ -65709,14 +65821,15 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (5-1):0] csr_d;
+reg [ (5-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
-
-
+wire break_d;
+reg break_x;
+
wire scall_d;
reg scall_x;
@@ -65729,14 +65842,16 @@ reg eret_m;
-
-
-
-
-
+
+wire bret_d;
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+
+
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -65888,11 +66003,11 @@ wire [ (32-1):0] cfg2;
reg [ (32-1):0] csr_read_data_x;
-wire [ ((32-2)+2-1):2] pc_f;
-wire [ ((32-2)+2-1):2] pc_d;
-wire [ ((32-2)+2-1):2] pc_x;
-wire [ ((32-2)+2-1):2] pc_m;
-wire [ ((32-2)+2-1):2] pc_w;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
@@ -65906,12 +66021,13 @@ wire [ (32-1):0] instruction_f;
wire [ (32-1):0] instruction_d;
-
-
-
-
-
+wire iflush;
+wire icache_stall_request;
+wire icache_restart_request;
+wire icache_refill_request;
+wire icache_refilling;
+
@@ -65937,25 +66053,32 @@ wire stall_wb_load;
-
-
-
-
-
-
-
-
+
+wire [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
+
-
-
+wire jtag_csr_write_enable;
+wire [ (32-1):0] jtag_csr_write_data;
+wire [ (5-1):0] jtag_csr;
+wire jtag_read_enable;
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
-
+
+wire jtag_break;
+
+
+
@@ -65985,10 +66108,11 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (32-2)+2-1:8] eba;
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+
reg [ (3-1):0] eid_x;
@@ -65998,34 +66122,41 @@ reg [ (3-1):0] eid_x;
-
-
-
-
-
-
-
+
+
+wire dc_ss;
+
+wire dc_re;
+wire bp_match;
+wire wp_match;
+wire exception_x;
+reg exception_m;
+wire debug_exception_x;
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
-
+
-wire exception_x;
-reg exception_m;
-reg exception_w;
-wire exception_q_w;
-
+
-
-
+wire reset_exception;
+
+
@@ -66033,9 +66164,10 @@ wire interrupt_exception;
-
-
+wire breakpoint_exception;
+wire watchpoint_exception;
+
@@ -66116,7 +66248,7 @@ endfunction
-lm32_instruction_unit_medium #(
+lm32_instruction_unit_medium_icache_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -66147,8 +66279,9 @@ lm32_instruction_unit_medium #(
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
+ .iflush (iflush),
+
@@ -66172,11 +66305,12 @@ lm32_instruction_unit_medium #(
-
-
-
-
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+
@@ -66186,11 +66320,12 @@ lm32_instruction_unit_medium #(
.pc_m (pc_m),
.pc_w (pc_w),
-
-
-
-
+ .icache_stall_request (icache_stall_request),
+ .icache_restart_request (icache_restart_request),
+ .icache_refill_request (icache_refill_request),
+ .icache_refilling (icache_refilling),
+
@@ -66211,9 +66346,10 @@ lm32_instruction_unit_medium #(
-
-
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+
@@ -66228,7 +66364,7 @@ lm32_instruction_unit_medium #(
);
-lm32_decoder_medium decoder (
+lm32_decoder_medium_icache_debug decoder (
.instruction (instruction_d),
@@ -66307,14 +66443,16 @@ lm32_decoder_medium decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+ .break_opcode (break_d),
+
.scall (scall_d),
.eret (eret_d),
-
+ .bret (bret_d),
+
@@ -66324,7 +66462,7 @@ lm32_decoder_medium decoder (
);
-lm32_load_store_unit_medium #(
+lm32_load_store_unit_medium_icache_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -66490,7 +66628,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium interrupt_unit (
+lm32_interrupt_medium_icache_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -66499,17 +66637,18 @@ lm32_interrupt_medium interrupt_unit (
.stall_x (stall_x),
-
-
-
- .exception (exception_q_w),
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+
+
.eret_q_x (eret_q_x),
-
+ .bret_q_x (bret_q_x),
+
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -66524,95 +66663,116 @@ lm32_interrupt_medium interrupt_unit (
-
+
+lm32_jtag_medium_icache_debug jtag (
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
-
-
-
-
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
-
-
-
-
+
+
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
-
-
+
+
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
+
+
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
-
-
+
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
-
-
-
-
-
-
-
+
+
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
-
-
-
-
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+
-
-
-
-
+
+lm32_debug_medium_icache_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
-
-
-
-
-
-
-
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .pc_x (pc_x),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_store_address_x (adder_result_x),
+ .csr_write_enable_x (csr_write_enable_q_x),
+ .csr_write_data (operand_1_x),
+ .csr_x (csr_x),
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
-
-
-
-
-
-
+
+
+
+ .eret_q_x (eret_q_x),
+ .bret_q_x (bret_q_x),
+ .stall_x (stall_x),
+ .exception_x (exception_x),
+ .q_x (q_x),
+
-
-
-
-
-
+
+
+ .dc_ss (dc_ss),
+
+ .dc_re (dc_re),
+ .bp_match (bp_match),
+ .wp_match (wp_match)
+ );
+
@@ -67057,8 +67217,9 @@ assign kill_f = ( (valid_d == 1'b1)
-
+ || (icache_refill_request == 1'b1)
+
@@ -67071,8 +67232,9 @@ assign kill_d = (branch_taken_m == 1'b1)
-
+ || (icache_refill_request == 1'b1)
+
@@ -67101,21 +67263,25 @@ assign kill_w = 1'b0
-
-
-
-
-
-
-
-
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
+ )
+ && (valid_x == 1'b1)
+ )
+
+ || (jtag_break == 1'b1)
+
+
+ ;
+
-
+assign watchpoint_exception = wp_match == 1'b1;
+
@@ -67139,38 +67305,17 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
-
-
-
-
-
-
-
-
-
-
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
+ ;
-
-
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+
+ || (reset_exception == 1'b1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign exception_x = (system_call_exception == 1'b1)
@@ -67184,8 +67329,9 @@ assign exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
@@ -67196,27 +67342,54 @@ assign exception_x = (system_call_exception == 1'b1)
;
+
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
always @(*)
begin
+
+
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
-
-
-
+
-
-
-
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
+ else
+
@@ -67228,10 +67401,11 @@ begin
-
-
-
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
+
@@ -67243,8 +67417,9 @@ begin
if ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
)
eid_x = 3'h6;
@@ -67280,18 +67455,19 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
-
-
-
-
-
-
-
-
-
-
-
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
+ )
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
+ )
+ && (kill_d == 1'b0)
+ )
+
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -67353,16 +67529,14 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
-
-
-
- || (I_CYC_O == 1'b1)
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
-
+
+
+
@@ -67395,21 +67569,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
@@ -67420,12 +67597,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
@@ -67441,19 +67618,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
-
-
@@ -67462,18 +67632,25 @@ assign cfg = {
-
-
- 1'b0,
+ 1'b1,
+
+
+
+ 1'b1,
+
- 1'b0,
+
+
+ 1'b1,
+
+
@@ -67546,19 +67723,22 @@ assign cfg2 = {
-
-
-
-
-
-
-
-
-
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 5'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
-
+
+
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
+
+ ;
+
@@ -67574,7 +67754,7 @@ assign cfg2 = {
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (5-1):0];
always @(*)
@@ -67582,27 +67762,29 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
-
+ 5'h9: csr_read_data_x = {deba, 8'h00};
+
-
-
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
+
- 3'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -67616,36 +67798,40 @@ end
always @(posedge clk_i )
begin
if (rst_i == 1'b1)
- eba <= eba_reset[ (32-2)+2-1:8];
+ eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (32-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
end
end
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ end
+end
+
@@ -67682,7 +67868,8 @@ end
-
+
+
@@ -67697,19 +67884,20 @@ end
-
-
-
-
-
-
-
+always @(*)
+begin
+ if (icache_refill_request == 1'b1)
+ valid_a = 1'b0;
+ else if (icache_restart_request == 1'b1)
+ valid_a = 1'b1;
+ else
+ valid_a = !icache_refilling;
+end
-
-
-
+
+
@@ -67721,7 +67909,6 @@ end
-
always @(posedge clk_i )
@@ -67738,11 +67925,11 @@ begin
begin
if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= 1'b1;
+ valid_f <= valid_a;
+
+
else if (stall_f == 1'b0)
valid_f <= 1'b0;
@@ -67787,7 +67974,7 @@ begin
operand_0_x <= { 32{1'b0}};
operand_1_x <= { 32{1'b0}};
store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (32-2){1'b0}};
+ branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
x_result_sel_csr_x <= 1'b0;
@@ -67824,7 +68011,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 5{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -67847,14 +68034,16 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
-
+ break_x <= 1'b0;
+
scall_x <= 1'b0;
eret_x <= 1'b0;
-
+ bret_x <= 1'b0;
+
@@ -67863,7 +68052,7 @@ begin
csr_write_enable_x <= 1'b0;
operand_m <= { 32{1'b0}};
- branch_target_m <= { (32-2){1'b0}};
+ branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
m_result_sel_compare_m <= 1'b0;
@@ -67896,9 +68085,10 @@ begin
-
-
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
+
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -67910,12 +68100,12 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
-
-
- exception_w <= 1'b0;
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
+
+
@@ -67935,7 +68125,7 @@ begin
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
@@ -67994,8 +68184,9 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+ break_x <= break_d;
+
scall_x <= scall_d;
@@ -68004,8 +68195,9 @@ begin
eret_x <= eret_d;
-
+ bret_x <= bret_d;
+
write_enable_x <= write_enable_d;
end
@@ -68057,40 +68249,40 @@ begin
+
-
-
-
-
-
-
-
-
- if (exception_x == 1'b1)
+ if (non_debug_exception_x == 1'b1)
write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
+
+
+
+
+
condition_met_m <= condition_met_x;
-
-
-
-
-
-
-
-
-
-
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
+ branch_target_m <= {deba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= {eba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= branch_target_x;
+
+
@@ -68102,14 +68294,16 @@ begin
eret_m <= eret_q_x;
-
+ bret_m <= bret_q_x;
+
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ debug_exception_m <= debug_exception_x;
+ non_debug_exception_m <= non_debug_exception_x;
+
end
@@ -68155,12 +68349,12 @@ begin
write_enable_w <= write_enable_m;
-
-
-
- exception_w <= exception_m;
+ debug_exception_w <= debug_exception_m;
+ non_debug_exception_w <= non_debug_exception_m;
+
+
@@ -68568,7 +68762,7 @@ endmodule
-
+
@@ -68705,7 +68899,7 @@ endmodule
-module lm32_load_store_unit_medium (
+module lm32_load_store_unit_medium_icache_debug (
clk_i,
rst_i,
@@ -69782,7 +69976,7 @@ endmodule
-
+
@@ -70017,7 +70211,7 @@ endmodule
-module lm32_decoder_medium (
+module lm32_decoder_medium_icache_debug (
instruction,
@@ -70096,14 +70290,16 @@ module lm32_decoder_medium (
bi_conditional,
bi_unconditional,
-
+ break_opcode,
+
scall,
eret,
-
+ bret,
+
@@ -70187,8 +70383,8 @@ output [ (5-1):0] write_idx;
wire [ (5-1):0] write_idx;
output [ (32-1):0] immediate;
wire [ (32-1):0] immediate;
-output [ ((32-2)+2-1):2] branch_offset;
-wire [ ((32-2)+2-1):2] branch_offset;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
@@ -70237,18 +70433,20 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+output break_opcode;
+wire break_opcode;
+
output scall;
wire scall;
output eret;
wire eret;
-
-
+output bret;
+wire bret;
+
@@ -70270,6 +70468,90 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+
+
+
+
+wire op_mul;
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+wire op_sextb;
+wire op_sexth;
+
+
+wire op_sh;
+
+
+wire op_sl;
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+wire shift;
+
+
+
+
+
+
+
+
+wire sext;
+
+
+
@@ -70425,9 +70707,8 @@ assign sext = op_sextb | op_sexth;
+
-assign multiply = op_mul;
-
@@ -70602,14 +70883,16 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+assign break_opcode = op_raise & ~instruction[2];
+
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+assign bret = op_b & (instruction[25:21] == 5'd31);
+
@@ -70863,7 +71146,7 @@ endmodule
-
+
@@ -70998,210 +71281,187 @@ endmodule
-
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+module lm32_icache_medium_icache_debug (
+ clk_i,
+ rst_i,
+ stall_a,
+ stall_f,
+ address_a,
+ address_f,
+ read_enable_f,
+ refill_ready,
+ refill_data,
+ iflush,
+
+
+
+ valid_d,
+ branch_predict_taken_d,
-
-
-
-
-
-
-
+ stall_request,
+ restart_request,
+ refill_request,
+ refill_address,
+ refilling,
+ inst
+ );
-
-
-
-
-
+parameter associativity = 1;
+parameter sets = 512;
+parameter bytes_per_line = 16;
+parameter base_address = 0;
+parameter limit = 0;
-
-
-
-
-
-
-
-
-
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
-
-
+input clk_i;
+input rst_i;
-
-
+input stall_a;
+input stall_f;
-
-
+input valid_d;
+input branch_predict_taken_d;
-
-
-
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input read_enable_f;
-
-
+input refill_ready;
+input [ (32-1):0] refill_data;
-
-
+input iflush;
+
+
-
-
-
-
-
-
-
-
-
-
-
-
+output stall_request;
+wire stall_request;
+output restart_request;
+reg restart_request;
+output refill_request;
+wire refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output refilling;
+reg refilling;
+output [ (32-1):0] inst;
+wire [ (32-1):0] inst;
-
-
-
-
-
-
-
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+
+genvar i;
+
+
-
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@@ -71210,214 +71470,310 @@ endmodule
-
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-
-
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
-
-
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
-
-
-
-
-
-
-
-
-
-
+ generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : memories
+
+ lm32_ram
+ #(
+
+ .data_width (32),
+ .address_width ( (addr_offset_width+addr_set_width))
+)
+ way_0_data_ram
+ (
+
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (dmem_read_address),
+ .enable_read (enable),
+ .write_address (dmem_write_address),
+ .enable_write ( 1'b1),
+ .write_enable (way_mem_we[i]),
+ .write_data (refill_data),
+
+ .read_data (way_data[i])
+ );
+
+ lm32_ram
+ #(
+
+ .data_width ( (addr_tag_width+1)),
+ .address_width ( addr_set_width)
-
-
-
-
-
-
-
-
+ )
+ way_0_tag_ram
+ (
+
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (tmem_read_address),
+ .enable_read (enable),
+ .write_address (tmem_write_address),
+ .enable_write ( 1'b1),
+ .write_enable (way_mem_we[i] | flushing),
+ .write_data (tmem_write_data),
+
+ .read_data ({way_tag[i], way_valid[i]})
+ );
+
+ end
+endgenerate
+
+
+
+
+
+
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+ end
+endgenerate
+
+
+generate
+ if (associativity == 1)
+ begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+ end
+ else if (associativity == 2)
+ begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+ end
+endgenerate
+
+
+generate
+ if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+ else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
-
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
-
-
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing
+ ? flush_set
+ : refill_address[ addr_set_msb:addr_set_lsb];
-
-
-
+generate
+ if (bytes_per_line > 4)
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+ else
+assign last_refill = 1'b1;
+endgenerate
-
-
-
-
+assign enable = (stall_a == 1'b0);
+generate
+ if (associativity == 1)
+ begin : we_1
+assign way_mem_we[0] = (refill_ready == 1'b1);
+ end
+ else
+ begin : we_2
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+ end
+endgenerate
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
-
-
-
-
-
-
-
-
-
-
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
-
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
+
-
-
-
-
-
+generate
+ if (associativity >= 2)
+ begin : way_select
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+ else
+ begin
+ if (miss == 1'b1)
+ refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+ end
+end
+ end
+endgenerate
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
+ else
+ refilling <= refill;
+end
-
-
-
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+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'b0001;
+ flush_set <= { addr_set_width{1'b1}};
+ refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
+ end
+ else
+ begin
+ case (state)
+ 4'b0001:
+ begin
+ if (flush_set == { addr_set_width{1'b0}})
+ state <= 4'b0100;
+ flush_set <= flush_set - 1'b1;
+ end
+
-
-
-
+ 4'b0010:
+ begin
+ if (flush_set == { addr_set_width{1'b0}})
+
-
+
+ state <= 4'b0100;
-
-
-
-
+ flush_set <= flush_set - 1'b1;
+ end
-
-
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+ 4'b0100:
+ begin
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
+ begin
+ refill_address <= address_f;
+ state <= 4'b0010;
+ end
+ else if (miss == 1'b1)
+ begin
+ refill_address <= address_f;
+ state <= 4'b1000;
+ end
+ end
-
-
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+ 4'b1000:
+ begin
+ if (refill_ready == 1'b1)
+ begin
+ if (last_refill == 1'b1)
+ begin
+ restart_request <= 1'b1;
+ state <= 4'b0100;
+ end
+ end
+ end
-
-
-
+ endcase
+ end
+end
-
+generate
+ if (bytes_per_line > 4)
+ begin
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
-
-
-
-
-
-
+ 4'b0100:
+ begin
+ if (iflush == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else if (miss == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
-
-
-
-
-
-
-
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-
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+ 4'b1000:
+ begin
+ if (refill_ready == 1'b1)
+ refill_offset <= refill_offset + 1'b1;
+ end
+ endcase
+ end
+end
+ end
+endgenerate
+endmodule
-
-
+
@@ -71638,7 +71994,7 @@ endmodule
-
+
@@ -72465,7 +72821,7 @@ endmodule
-
+
@@ -72601,135 +72957,160 @@ endmodule
-
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+
+
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+
+
+
+module lm32_debug_medium_icache_debug (
+ clk_i,
+ rst_i,
+ pc_x,
+ load_x,
+ store_x,
+ load_store_address_x,
+ csr_write_enable_x,
+ csr_write_data,
+ csr_x,
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
-
+
+ eret_q_x,
+ bret_q_x,
+ stall_x,
+ exception_x,
+ q_x,
+
+
+
-
-
-
-
+
+
+ dc_ss,
+
+
+ dc_re,
+ bp_match,
+ wp_match
+ );
-
-
+parameter breakpoints = 0;
+parameter watchpoints = 0;
-
-
+input clk_i;
+input rst_i;
-
-
-
-
-
-
-
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input load_x;
+input store_x;
+input [ (32-1):0] load_store_address_x;
+input csr_write_enable_x;
+input [ (32-1):0] csr_write_data;
+input [ (5-1):0] csr_x;
+
+
+input jtag_csr_write_enable;
+input [ (32-1):0] jtag_csr_write_data;
+input [ (5-1):0] jtag_csr;
+
+
+
+input eret_q_x;
+input bret_q_x;
+input stall_x;
+input exception_x;
+input q_x;
+
-
-
+
-
-
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+
+output dc_ss;
+reg dc_ss;
-
-
-
-
-
-
-
-
+output dc_re;
+reg dc_re;
+output bp_match;
+wire bp_match;
+output wp_match;
+wire wp_match;
-
+genvar i;
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg bp_e[0:breakpoints-1];
+wire [0:breakpoints-1]bp_match_n;
-
-
-
+reg [ 1:0] wpc_c[0:watchpoints-1];
+reg [ (32-1):0] wp[0:watchpoints-1];
+wire [0:watchpoints]wp_match_n;
+
+wire debug_csr_write_enable;
+wire [ (32-1):0] debug_csr_write_data;
+wire [ (5-1):0] debug_csr;
+
+
-
-
-
+
+reg [ 2:0] state;
-
+
-
@@ -72737,48 +73118,15 @@ endmodule
-
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@@ -72787,132 +73135,223 @@ endmodule
-
-
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-
-
-
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
-
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+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+ end
+endgenerate
+generate
+
+ if (breakpoints > 0)
+assign bp_match = (|bp_match_n) || (state == 3'b011);
+ else
+assign bp_match = state == 3'b011;
+
+
-
-
-
-
-
-
-
+
+
+
+endgenerate
-
-
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+ end
+endgenerate
+generate
+ if (watchpoints > 0)
+assign wp_match = |wp_match_n;
+ else
+assign wp_match = 1'b0;
+endgenerate
-
-
-
-
-
-
-
+
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
+
+
+
+
+
+
+
+
+
+
+
+
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ begin
+ bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_e[i] <= debug_csr_write_data[0];
+ end
+ end
+end
+ end
+endgenerate
+
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ wp[i] <= { 32{1'bx}};
+ wpc_c[i] <= 2'b00;
+ end
+ else
+ begin
+ if (debug_csr_write_enable == 1'b1)
+ begin
+ if (debug_csr == 5'h8)
+ wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+ if (debug_csr == 5'h18 + i)
+ wp[i] <= debug_csr_write_data;
+ end
+ end
+end
+ end
+endgenerate
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ dc_re <= debug_csr_write_data[1];
+ end
+end
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 3'b000;
+ dc_ss <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ begin
+ dc_ss <= debug_csr_write_data[0];
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
+ else
+ state <= 3'b001;
+ end
+ case (state)
+ 3'b001:
+ begin
-
-
-
-
-
-
-
-
-
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
+ )
+ && (stall_x == 1'b0)
+ )
+ state <= 3'b010;
+ end
+ 3'b010:
+ begin
-
-
-
-
-
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
+ end
+ 3'b011:
+ begin
-
+
-
-
-
-
-
-
-
-
+
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ begin
+ dc_ss <= 1'b0;
+ state <= 3'b100;
+ end
+ end
+ 3'b100:
+ begin
-
+
-
-
-
-
-
-
+ state <= 3'b000;
+ end
+ endcase
+ end
+end
+
+endmodule
+
@@ -73148,7 +73587,7 @@ endmodule
-
+
@@ -73285,7 +73724,7 @@ endmodule
-module lm32_instruction_unit_medium (
+module lm32_instruction_unit_medium_icache_debug (
clk_i,
rst_i,
@@ -73310,8 +73749,9 @@ module lm32_instruction_unit_medium (
branch_mispredict_taken_m,
branch_target_m,
-
+ iflush,
+
@@ -73335,11 +73775,12 @@ module lm32_instruction_unit_medium (
-
-
-
-
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+
@@ -73349,11 +73790,12 @@ module lm32_instruction_unit_medium (
pc_m,
pc_w,
-
-
-
-
+ icache_stall_request,
+ icache_restart_request,
+ icache_refill_request,
+ icache_refilling,
+
@@ -73374,9 +73816,10 @@ module lm32_instruction_unit_medium (
-
-
+ jtag_read_data,
+ jtag_access_complete,
+
@@ -73422,7 +73865,7 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((32-2)+2-1):2] branch_predict_address_d;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
@@ -73432,11 +73875,12 @@ input [ ((32-2)+2-1):2] branch_predict_address_d;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((32-2)+2-1):2] branch_target_m;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
+input iflush;
+
@@ -73462,38 +73906,40 @@ input i_rty_i;
-
-
-
-
+input jtag_read_enable;
+input jtag_write_enable;
+input [ 7:0] jtag_write_data;
+input [ (32-1):0] jtag_address;
+
-output [ ((32-2)+2-1):2] pc_f;
-reg [ ((32-2)+2-1):2] pc_f;
-output [ ((32-2)+2-1):2] pc_d;
-reg [ ((32-2)+2-1):2] pc_d;
-output [ ((32-2)+2-1):2] pc_x;
-reg [ ((32-2)+2-1):2] pc_x;
-output [ ((32-2)+2-1):2] pc_m;
-reg [ ((32-2)+2-1):2] pc_m;
-output [ ((32-2)+2-1):2] pc_w;
-reg [ ((32-2)+2-1):2] pc_w;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
-
-
-
-
-
-
+output icache_stall_request;
+wire icache_stall_request;
+output icache_restart_request;
+wire icache_restart_request;
+output icache_refill_request;
+wire icache_refill_request;
+output icache_refilling;
+wire icache_refilling;
+
@@ -73506,11 +73952,11 @@ reg [ ((32-2)+2-1):2] pc_w;
output [ (32-1):0] i_dat_o;
-
-
-wire [ (32-1):0] i_dat_o;
+reg [ (32-1):0] i_dat_o;
+
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -73518,21 +73964,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
-
-
-wire [ (4-1):0] i_sel_o;
+reg [ (4-1):0] i_sel_o;
+
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-wire i_we_o;
+reg i_we_o;
+
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -73544,11 +73990,12 @@ wire [ (2-1):0] i_bte_o;
-
-
-
-
+output [ 7:0] jtag_read_data;
+reg [ 7:0] jtag_read_data;
+output jtag_access_complete;
+wire jtag_access_complete;
+
@@ -73569,31 +74016,30 @@ reg [ (32-1):0] instruction_d;
-reg [ ((32-2)+2-1):2] pc_a;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-
-
-
-
-
-
-
-
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+
-reg [ (32-1):0] wb_data_f;
+wire icache_read_enable_f;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+reg icache_refill_ready;
+reg [ (32-1):0] icache_refill_data;
+wire [ (32-1):0] icache_data_f;
+wire [ (3-1):0] first_cycle_type;
+wire [ (3-1):0] next_cycle_type;
+wire last_word;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+
+
+
@@ -73613,8 +74059,9 @@ reg [ (32-1):0] wb_data_f;
-
+reg jtag_access;
+
@@ -73731,35 +74178,36 @@ endfunction
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+lm32_icache_medium_icache_debug #(
+ .associativity (associativity),
+ .sets (sets),
+ .bytes_per_line (bytes_per_line),
+ .base_address (base_address),
+ .limit (limit)
+ ) icache (
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_a (stall_a),
+ .stall_f (stall_f),
+ .branch_predict_taken_d (branch_predict_taken_d),
+ .valid_d (valid_d),
+ .address_a (pc_a),
+ .address_f (pc_f),
+ .read_enable_f (icache_read_enable_f),
+ .refill_ready (icache_refill_ready),
+ .refill_data (icache_refill_data),
+ .iflush (iflush),
-
+ .stall_request (icache_stall_request),
+ .restart_request (icache_restart_request),
+ .refill_request (icache_refill_request),
+ .refill_address (icache_refill_address),
+ .refilling (icache_refilling),
+ .inst (icache_data_f)
+ );
+
@@ -73768,16 +74216,19 @@ endfunction
-
-
-
+
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+
+
-
+
-
-
+
+ ;
+
@@ -73805,10 +74256,11 @@ begin
pc_a = branch_predict_address_d;
else
-
-
-
+ if (icache_restart_request == 1'b1)
+ pc_a = restart_address;
+ else
+
pc_a = pc_f + 1'b1;
end
@@ -73821,25 +74273,25 @@ end
-
-
-
+
+
+assign instruction_f = icache_data_f;
+
-
+
+
+
-assign instruction_f = wb_data_f;
-
-
@@ -73847,11 +74299,11 @@ assign instruction_f = wb_data_f;
-
-assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
-assign i_sel_o = 4'b1111;
+
+
+
+
assign i_bte_o = 2'b00;
@@ -73860,31 +74312,32 @@ assign i_bte_o = 2'b00;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+generate
+ case (bytes_per_line)
+ 4:
+ begin
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
+assign first_address = icache_refill_address;
+ end
+ 8:
+ begin
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+ end
+ 16:
+ begin
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+ end
+ endcase
+endgenerate
+
@@ -73897,10 +74350,10 @@ begin
if (rst_i == 1'b1)
begin
pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (32-2){1'b0}};
- pc_x <= { (32-2){1'b0}};
- pc_m <= { (32-2){1'b0}};
- pc_w <= { (32-2){1'b0}};
+ pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
@@ -73918,13 +74371,14 @@ end
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ else
+ begin
+
@@ -73936,14 +74390,18 @@ end
-
-
-
-
-
+
+
+ if (icache_refill_request == 1'b1)
+ restart_address <= icache_refill_address;
+
+
+ end
+end
+
@@ -73962,125 +74420,138 @@ end
-
-
-
-
-
-
-
-
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+always @(*)
+begin
+ case (jtag_address[1:0])
+ 2'b00: jtag_read_data = i_dat_i[ 31:24];
+ 2'b01: jtag_read_data = i_dat_i[ 23:16];
+ 2'b10: jtag_read_data = i_dat_i[ 15:8];
+ 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ endcase
+end
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= { 32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= { 32{1'b0}};
+ icache_refill_ready <= 1'b0;
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
-
-
-
-
-
-
-
-
-
+ end
+ else
+ begin
+ icache_refill_ready <= 1'b0;
+ if (i_cyc_o == 1'b1)
+ begin
-
-
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ begin
+
+
+ if (jtag_access == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
+ end
+ else
-
-
-
-
-
-
-
-
-
-
-
+ begin
+ if (last_word == 1'b1)
+ begin
-
-
-
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
+ end
-
-
+ i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+ i_cti_o <= next_cycle_type;
-
-
-
-
-
+ icache_refill_ready <= 1'b1;
+ icache_refill_data <= i_dat_i;
+ end
+ end
+
-
-
-
-
-
-
-
-
-
-
-
-
+ end
+ else
+ begin
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ begin
+
+
+ i_sel_o <= 4'b1111;
+
+ i_adr_o <= {first_address, 2'b00};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_cti_o <= first_cycle_type;
+
+
-
+
+ end
+
+
+ else
+ begin
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ begin
+ case (jtag_address[1:0])
+ 2'b00: i_sel_o <= 4'b1000;
+ 2'b01: i_sel_o <= 4'b0100;
+ 2'b10: i_sel_o <= 4'b0010;
+ 2'b11: i_sel_o <= 4'b0001;
+ endcase
+ i_adr_o <= jtag_address;
+ i_dat_o <= {4{jtag_write_data}};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_we_o <= jtag_write_enable;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
+ end
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
@@ -74089,92 +74560,85 @@ end
-
-
-
+ end
+ end
+end
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- wb_data_f <= { 32{1'b0}};
-
+
+
+
+
+
+
+
+
+
-
- end
- else
- begin
+
+
+
+
+
- if (i_cyc_o == 1'b1)
- begin
- if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
- begin
+
+
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
+
+
- wb_data_f <= i_dat_i;
- end
-
+
+
+
-
- end
- else
- begin
+
+
+
- if ( (stall_a == 1'b0)
-
-
+
+
- )
- begin
+
+
-
+
-
- i_adr_o <= {pc_a, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
-
+
+
+
+
-
- end
- else
- begin
- if ( (stall_a == 1'b0)
-
+
+
+
+
+
-
- )
- begin
-
+
+
+
+
+
+
+
+
- end
- end
- end
- end
-end
-
@@ -74420,7 +74884,7 @@ endmodule
-
+
@@ -74555,443 +75019,523 @@ endmodule
-
-
-
+
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module lm32_jtag_medium_icache_debug (
-
-
-
-
-
-
+ clk_i,
+ rst_i,
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
+
+ csr,
+ csr_write_enable,
+ csr_write_data,
+ stall_x,
-
-
-
-
+
+
+ jtag_read_data,
+ jtag_access_complete,
-
-
+
+
+ exception_q_w,
-
+
+
+ jtx_csr_read_data,
+ jrx_csr_read_data,
-
-
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
-
-
-
-
-
-
-
+
+
+ jtag_break,
+ jtag_reset,
-
-
-
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d
+ );
-
-
+input clk_i;
+input rst_i;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
+
+input [ (5-1):0] csr;
+input csr_write_enable;
+input [ (32-1):0] csr_write_data;
+input stall_x;
-
-
-
-
+
+
+input [ 7:0] jtag_read_data;
+input jtag_access_complete;
-
-
+
+
+input exception_q_w;
-
-
-
-
-
-
+
+output [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+output jtag_csr_write_enable;
+reg jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;
+wire [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;
+wire [ (5-1):0] jtag_csr;
+output jtag_read_enable;
+reg jtag_read_enable;
+output jtag_write_enable;
+reg jtag_write_enable;
+output [ 7:0] jtag_write_data;
+wire [ 7:0] jtag_write_data;
+output [ (32-1):0] jtag_address;
+wire [ (32-1):0] jtag_address;
-
-
-
-
-
-
-
-
+output jtag_break;
+reg jtag_break;
+output jtag_reset;
+reg jtag_reset;
+
+output [ 7:0] jtag_reg_d;
+reg [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
-
-
-
-
+reg rx_update;
+reg rx_update_r;
+reg rx_update_r_r;
+reg rx_update_r_r_r;
-
-
-
-
-
-
-
+wire [ 7:0] rx_byte;
+wire [2:0] rx_addr;
-
-
-
-
-
-
-
+
+reg [ 7:0] uart_tx_byte;
+reg uart_tx_valid;
+reg [ 7:0] uart_rx_byte;
+reg uart_rx_valid;
+
-
+reg [ 3:0] command;
+
+reg [ 7:0] jtag_byte_0;
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;
+
+reg [ 3:0] state;
-
-
-
-
-
-
-
-
-
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
-
-
-
-
-
-
-
-
+
+
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
+
+
+
-
+assign jtag_reg_addr_d[2] = processing;
+
-
+
+
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ rx_update <= 1'b0;
+ rx_update_r <= 1'b0;
+ rx_update_r_r <= 1'b0;
+ rx_update_r_r_r <= 1'b0;
+ end
+ else
+ begin
+ rx_update <= jtag_update;
+ rx_update_r <= rx_update;
+ rx_update_r_r <= rx_update_r;
+ rx_update_r_r_r <= rx_update_r_r;
+ end
+end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'h0;
+ command <= 4'b0000;
+ jtag_reg_d <= 8'h00;
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
+
-
-
-
-
-
-
-
+
-
-
-
-
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
+
-
-
-
-
-
-
-
+
+
+ uart_tx_byte <= 8'h00;
+ uart_tx_valid <= 1'b0;
+ uart_rx_byte <= 8'h00;
+ uart_rx_valid <= 1'b0;
+
+
+ end
+ else
+ begin
+
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+ begin
+ case (csr)
+ 5'he:
+ begin
-
-
+ uart_tx_byte <= csr_write_data[ 7:0];
+ uart_tx_valid <= 1'b1;
+ end
+ 5'hf:
+ begin
+ uart_rx_valid <= 1'b0;
+ end
+ endcase
+ end
+
+
+
-
-
-
-
+ if (exception_q_w == 1'b1)
+ begin
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+ case (state)
+ 4'h0:
+ begin
-
-
-
-
-
-
-
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ command <= rx_byte[7:4];
+ case (rx_addr)
+
+
+ 3'b000:
+ begin
+ case (rx_byte[7:4])
+
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 4'h6;
+ end
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 5;
+ end
+ 4'b0101:
+ state <= 4'h1;
+
-
-
-
-
-
-
-
-
-
-
+ 4'b0110:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
+ jtag_break <= 1'b1;
+ end
+ 4'b0111:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
+
+ jtag_reset <= 1'b1;
+ end
+ endcase
+ end
+
+
+
+
+ 3'b001:
+ begin
+ uart_rx_byte <= rx_byte;
+ uart_rx_valid <= 1'b1;
+ end
+ 3'b010:
+ begin
+ jtag_reg_d <= uart_tx_byte;
+ uart_tx_valid <= 1'b0;
+ end
+
+ default:
+ ;
+ endcase
+ end
+ end
+ 4'h1:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_0 <= rx_byte;
+ state <= 4'h2;
+ end
+ end
+ 4'h2:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_1 <= rx_byte;
+ state <= 4'h3;
+ end
+ end
+ 4'h3:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_2 <= rx_byte;
+ state <= 4'h4;
+ end
+ end
+ 4'h4:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_3 <= rx_byte;
+ if (command == 4'b0001)
+ state <= 4'h6;
+ else
+ state <= 4'h5;
+ end
+ end
+ 4'h5:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_4 <= rx_byte;
+ state <= 4'h6;
+ end
+ end
+ 4'h6:
+ begin
+ case (command)
+ 4'b0001,
+ 4'b0011:
+ begin
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0010,
+ 4'b0100:
+ begin
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0101:
+ begin
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
+ end
+ endcase
+ end
+ 4'h7:
+ begin
+ if (jtag_access_complete == 1'b1)
+ begin
+ jtag_read_enable <= 1'b0;
+ jtag_reg_d <= jtag_read_data;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+ end
+ 4'h8:
+ begin
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+
+ endcase
+ end
+end
+
+endmodule
+
@@ -75209,7 +75753,7 @@ endmodule
-
+
@@ -75346,7 +75890,7 @@ endmodule
-module lm32_interrupt_medium (
+module lm32_interrupt_medium_icache_debug (
clk_i,
rst_i,
@@ -75355,17 +75899,18 @@ module lm32_interrupt_medium (
stall_x,
-
-
-
- exception,
+ non_debug_exception,
+ debug_exception,
+
+
eret_q_x,
-
+ bret_q_x,
+
csr,
csr_write_data,
@@ -75394,20 +75939,21 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
-
-input exception;
+input non_debug_exception;
+input debug_exception;
+
+
input eret_q_x;
-
+input bret_q_x;
+
-input [ (3-1):0] csr;
+input [ (5-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -75428,14 +75974,18 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
reg ie;
reg eie;
-
+reg bie;
+
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -75455,11 +76005,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
@@ -75473,19 +76023,19 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -75496,18 +76046,18 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 5'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -75536,8 +76086,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -75549,13 +76100,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -75563,14 +76122,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -75588,26 +76139,28 @@ always @(posedge clk_i )
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -75624,8 +76177,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -75635,13 +76189,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -75649,14 +76211,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -75672,24 +76226,26 @@ always @(posedge clk_i )
end
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -76814,7 +77370,7 @@ endmodule
-
+
@@ -77485,7 +78041,7 @@ endmodule
-
+
@@ -77931,6 +78487,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d;
reg store_x;
reg store_m;
@@ -77961,6 +78520,7 @@ wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
+
@@ -78027,8 +78587,8 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (4 -1):0] csr_d;
+reg [ (4 -1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
@@ -78317,6 +78877,8 @@ reg [ (3-1):0] eid_x;
+
+
@@ -79882,7 +80444,7 @@ assign cfg2 = {
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (4 -1):0];
always @(*)
@@ -79890,17 +80452,17 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 4 'h0,
+ 4 'h1,
+ 4 'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 4 'h6: csr_read_data_x = cfg;
+ 4 'h7: csr_read_data_x = {eba, 8'h00};
@@ -79910,7 +80472,7 @@ begin
- 3'ha: csr_read_data_x = cfg2;
+ 4 'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -79927,7 +80489,7 @@ begin
eba <= eba_reset[ (32-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 4 'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (32-2)+2-1:8];
@@ -80130,7 +80692,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 4 {1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -80861,7 +81423,7 @@ endmodule
-
+
@@ -82075,7 +82637,7 @@ endmodule
-
+
@@ -82557,6 +83119,86 @@ wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+
+
+
+
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+
+
+
+
+
+
+
+
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+
+
+
+
+
+wire op_sh;
+
+
+
+
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+
+
+
+
+
+
+wire shift;
+
+
+
+
+
+
+
@@ -83141,7 +83783,7 @@ endmodule
-
+
@@ -83916,7 +84558,7 @@ endmodule
-
+
@@ -84743,7 +85385,7 @@ endmodule
-
+
@@ -85426,7 +86068,7 @@ endmodule
-
+
@@ -86698,7 +87340,7 @@ endmodule
-
+
@@ -87487,7 +88129,7 @@ endmodule
-
+
@@ -87685,7 +88327,7 @@ input eret_q_x;
-input [ (3-1):0] csr;
+input [ (4 -1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -87706,6 +88348,9 @@ reg [ (32-1):0] csr_read_data;
wire [interrupts-1:0] asserted;
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
@@ -87751,7 +88396,7 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
@@ -87762,8 +88407,8 @@ begin
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 4 'h2: csr_read_data = ip;
+ 4 'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -87774,7 +88419,7 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 4 'h0: csr_read_data = {{ 32-3{1'b0}},
@@ -87785,7 +88430,7 @@ begin
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 4 'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -87874,7 +88519,7 @@ always @(posedge clk_i )
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
@@ -87883,9 +88528,9 @@ always @(posedge clk_i )
end
- if (csr == 3'h1)
+ if (csr == 4 'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -87958,7 +88603,7 @@ always @(posedge clk_i )
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 4 'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
@@ -87967,7 +88612,7 @@ always @(posedge clk_i )
end
- if (csr == 3'h2)
+ if (csr == 4 'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
diff --git a/modules/wishbone/wb_lm32/src/lm32_cpu.v b/modules/wishbone/wb_lm32/src/lm32_cpu.v
index 3810ecf1..e9276e58 100644
--- a/modules/wishbone/wb_lm32/src/lm32_cpu.v
+++ b/modules/wishbone/wb_lm32/src/lm32_cpu.v
@@ -341,6 +341,9 @@ reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
+wire q_m;
+wire load_q_m;
+wire store_q_m;
wire store_d; // Indicates a store instruction
reg store_x;
reg store_m;
@@ -371,6 +374,7 @@ wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be sele
wire x_result_sel_csr_d; // Select X stage result from CSRs
reg x_result_sel_csr_x;
`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire q_d;
wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
reg x_result_sel_mc_arith_x;
`endif
@@ -689,6 +693,8 @@ reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
wire dc_ss; // Is single-step enabled
`endif
wire dc_re; // Remap all exceptions
+wire bp_match;
+wire wp_match;
wire exception_x; // An exception occured in the X stage
reg exception_m; // An instruction that caused an exception is in the M stage
wire debug_exception_x; // Indicates if a debug exception has occured
diff --git a/modules/wishbone/wb_lm32/src/lm32_decoder.v b/modules/wishbone/wb_lm32/src/lm32_decoder.v
index d54375f0..57d50f70 100644
--- a/modules/wishbone/wb_lm32/src/lm32_decoder.v
+++ b/modules/wishbone/wb_lm32/src/lm32_decoder.v
@@ -308,6 +308,77 @@ wire sign_extend_immediate; // Whether the immediate should
wire select_high_immediate; // Whether to select the high immediate
wire select_call_immediate; // Whether to select the call immediate
+wire op_add;
+wire op_and;
+wire op_andhi;
+wire op_b;
+wire op_bi;
+wire op_be;
+wire op_bg;
+wire op_bge;
+wire op_bgeu;
+wire op_bgu;
+wire op_bne;
+wire op_call;
+wire op_calli;
+wire op_cmpe;
+wire op_cmpg;
+wire op_cmpge;
+wire op_cmpgeu;
+wire op_cmpgu;
+wire op_cmpne;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_divu;
+`endif
+wire op_lb;
+wire op_lbu;
+wire op_lh;
+wire op_lhu;
+wire op_lw;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_modu;
+`endif
+`ifdef LM32_MULTIPLY_ENABLED
+wire op_mul;
+`endif
+wire op_nor;
+wire op_or;
+wire op_orhi;
+wire op_raise;
+wire op_rcsr;
+wire op_sb;
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire op_sextb;
+wire op_sexth;
+`endif
+wire op_sh;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire op_sl;
+`endif
+wire op_sr;
+wire op_sru;
+wire op_sub;
+wire op_sw;
+wire op_user;
+wire op_wcsr;
+wire op_xnor;
+wire op_xor;
+
+wire arith;
+wire logical;
+wire cmp;
+wire bra;
+wire call;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire shift;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire shift;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire sext;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -396,7 +467,7 @@ assign shift_right = op_sr | op_sru;
`ifdef CFG_SIGN_EXTEND_ENABLED
assign sext = op_sextb | op_sexth;
`endif
-`ifdef LM32_MULTIPLY_ENABLED
+`ifdef CFG_MC_MULTIPLY_ENABLED
assign multiply = op_mul;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
diff --git a/modules/wishbone/wb_lm32/src/lm32_include.v b/modules/wishbone/wb_lm32/src/lm32_include.v
index c5f92526..40723d2c 100644
--- a/modules/wishbone/wb_lm32/src/lm32_include.v
+++ b/modules/wishbone/wb_lm32/src/lm32_include.v
@@ -183,7 +183,7 @@
`define LM32_CSR_WIDTH 4
`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
`else
-`define LM32_CSR_WIDTH 3
+`define LM32_CSR_WIDTH 4 // CFG2 is "a"
`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
`endif
`endif
diff --git a/modules/wishbone/wb_lm32/src/lm32_interrupt.v b/modules/wishbone/wb_lm32/src/lm32_interrupt.v
index c1b904bf..63352f3e 100644
--- a/modules/wishbone/wb_lm32/src/lm32_interrupt.v
+++ b/modules/wishbone/wb_lm32/src/lm32_interrupt.v
@@ -108,6 +108,9 @@ reg [`LM32_WORD_RNG] csr_read_data;
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//p_ragma attribute asserted preserve_signal true
wire [interrupts-1:0] interrupt_n_exception;
+wire [interrupts-1:0] ie_csr_read_data;
+wire [interrupts-1:0] ip_csr_read_data;
+wire [interrupts-1:0] im_csr_read_data;
// Interrupt CSRs
--
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