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Commit 2fe03ec0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tomasz Wlostowski
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changed the CPU profile in the testbench to medium

parent b32d5049
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testbench/wishbone/lm32_testsys/lm32_test_system.vhd
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...@@ -50,7 +50,7 @@ begin -- rtl ...@@ -50,7 +50,7 @@ begin -- rtl
U_CPU : xwb_lm32 U_CPU : xwb_lm32
generic map ( generic map (
g_profile => "minimal") g_profile => "medium")
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
......
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