testbench: added sample LM32 system

testbench/wishbone/lm32_testsys/Manifest.py

+action = "simulation"
+target = "xilinx"
+
+modules = {"local" : [ "../../.." ]	};
+files = ["main.sv", "lm32_test_system.vhd"]		

testbench/wishbone/lm32_testsys/lm32_test_system.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity lm32_test_system is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    gpio_b    : inout std_logic_vector(31 downto 0);
+    onewire_b : inout std_logic;
+    txd_o     : out   std_logic;
+    rxd_i     : in    std_logic
+    );
+
+end lm32_test_system;
+
+architecture rtl of lm32_test_system is  
+  constant c_cnx_slave_ports  : integer := 2;
+  constant c_cnx_master_ports : integer := 3;
+
+  constant c_peripherals : integer := 3;
+
+
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
+
+  signal cnx_master_in  : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
+  signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
+
+  signal periph_out : t_wishbone_master_out_array(0 to c_peripherals-1);
+  signal periph_in  : t_wishbone_master_in_array(0 to c_peripherals-1);
+
+
+  constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
+    (0 => x"00000000",                  -- CPU I-mem
+     1 => x"10000000",                  -- CPU D-mem
+     2 => x"20000000");                 -- Peripherals
+
+  constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
+    (0 => x"f0000000",
+     1 => x"f0000000",
+     2 => x"f0000000");
+
+  signal owr_en_slv, owr_in_slv : std_logic_vector(0 downto 0);
+  
+begin  -- rtl
+
+  U_CPU : xwb_lm32
+    generic map (
+      g_profile => "minimal")
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      irq_i     => x"00000000",
+      dwb_o     => cnx_slave_in(0),
+      dwb_i     => cnx_slave_out(0),
+      iwb_o     => cnx_slave_in(1),
+      iwb_i     => cnx_slave_out(1));
+
+  U_Intercon : xwb_crossbar
+    generic map (
+      g_num_masters => c_cnx_slave_ports,
+      g_num_slaves  => c_cnx_master_ports,
+      g_registered  => true)
+    port map (
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => cnx_slave_in,
+      slave_o       => cnx_slave_out,
+      master_i      => cnx_master_in,
+      master_o      => cnx_master_out,
+      cfg_address_i => c_cfg_base_addr,
+      cfg_mask_i    => c_cfg_base_mask);
+
+  U_DPRAM : xwb_dpram
+    generic map (
+      g_size                  => 8192,
+      g_init_file             => "sw/main.ram",
+      g_must_have_init_file   => true,
+      g_slave1_interface_mode => PIPELINED,
+      g_slave2_interface_mode => PIPELINED,
+      g_slave1_granularity    => BYTE,
+      g_slave2_granularity    => BYTE)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave1_i  => cnx_master_out(0),
+      slave1_o  => cnx_master_in(0),
+      slave2_i  => cnx_master_out(1),
+      slave2_o  => cnx_master_in(1));
+
+  U_peripheral_Fanout : xwb_bus_fanout
+    generic map (
+      g_num_outputs          => c_peripherals,
+      g_bits_per_slave       => 8,
+      g_address_granularity  => BYTE,
+      g_slave_interface_mode => PIPELINED)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => cnx_master_out(2),
+      slave_o   => cnx_master_in(2),
+      master_i  => periph_in,
+      master_o  => periph_out);
+
+  U_GPIO : xwb_gpio_port
+    generic map (
+      g_interface_mode         => CLASSIC,
+      g_address_granularity    => BYTE,
+      g_num_pins               => 32,
+      g_with_builtin_tristates => true)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => periph_out(0),
+      slave_o   => periph_in(0),
+      gpio_b    => gpio_b,
+      gpio_in_i => x"00000000"
+      );
+
+  U_UART : xwb_simple_uart
+    generic map (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      slave_i    => periph_out(1),
+      slave_o    => periph_in(1),
+      uart_rxd_i => rxd_i,
+      uart_txd_o => txd_o);
+
+  U_OneWire : xwb_onewire_master
+    generic map (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE,
+      g_num_ports           => 1)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => periph_out(2),
+      slave_o   => periph_in(2),
+      owr_en_o  => owr_en_slv,
+      owr_i     => owr_in_slv);
+
+  onewire_b <= '0' when owr_en_slv(0) = '1' else 'Z';
+  owr_in_slv(0) <= onewire_b;
+end rtl;

testbench/wishbone/lm32_testsys/main.sv

+`timescale 1ns/1ps
+
+module main;
+
+   reg clk_sys  =0;
+   reg rst_n    = 0;
+
+   always #5 clk_sys <= ~clk_sys;
+   
+   initial begin
+      repeat(3) @(posedge clk_sys);
+      rst_n  = 1;
+   end
+
+   
+   lm32_test_system
+     DUT (
+          .clk_sys_i (clk_sys),
+          .rst_n_i   (rst_n),
+          .gpio_b ()
+          );
+   
+                            
+
+endmodule // main
+
+

testbench/wishbone/lm32_testsys/run.do

+make
+
+vsim -L XilinxCoreLib -L secureip -L unisim work.main -voptargs="+acc"
+radix -hexadecimal
+do wave.do
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+run 100us
+wave zoomfull
\ No newline at end of file

testbench/wishbone/lm32_testsys/sw/Makefile

+PLATFORM = lm32
+
+OBJS_WRC = main.o uart.o target/lm32/crt0.o
+
+CROSS_COMPILE ?= /opt/gcc-lm32/bin/lm32-elf-
+CFLAGS_PLATFORM  = -mmultiply-enabled -mbarrel-shift-enabled  -I.
+LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled   -nostdlib -T target/lm32/ram.ld 
+
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+CFLAGS= $(CFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude $(PTPD_CFLAGS) -Iptp-noposix/PTPWRd 
+LDFLAGS= $(LDFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude 
+SIZE = $(CROSS_COMPILE)size
+OBJS=$(OBJS_PLATFORM) $(OBJS_WRC) $(OBJS_PTPD) $(OBJS_PTPD_FREE) 
+OUTPUT=main
+
+all: 		$(OBJS)
+				$(SIZE) -t $(OBJS)
+				${CC} -o $(OUTPUT).elf $(OBJS) $(LDFLAGS) 
+				${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
+				${OBJDUMP} -d $(OUTPUT).elf > $(OUTPUT)_disasm.S
+				./genraminit $(OUTPUT).bin 0 > $(OUTPUT).ram
+
+clean:	
+	rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram
+
+%.o:		%.c
+				${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $^ -o $@
+
+load:	all
+		./tools/lm32-loader $(OUTPUT).bin
+
+tools:
+			make -C tools
+		
+fpga:
+		- killall -9 vuart_console
+		../loadfile ../spec_top.bin
+		./tools/zpu-loader $(OUTPUT).bin

testbench/wishbone/lm32_testsys/sw/board.h

+#ifndef __BOARD_H
+#define __BOARD_H
+
+#define BASE_GPIO 	0x20000000
+
+static inline int delay(int x)
+{
+  while(x--) asm volatile("nop");
+}
+  
+#endif

testbench/wishbone/lm32_testsys/sw/genraminit.c

+#include <stdio.h>
+#include <stdlib.h>
+
+main(int argc, char *argv[])
+{
+	if(argc < 3) return -1;
+	FILE *f = fopen(argv[1],"rb");
+	if(!f) return -1;
+	unsigned char x[4];
+	int i=0;
+	int n = atoi(argv[2]);
+	
+	while(!feof(f))
+	{
+		fread(x,1,4,f);
+		printf("write %x %02X%02X%02X%02X\n", i++, x[0],x[1],x[2],x[3]);
+	}
+	
+	for(;i<n;)
+	{
+		printf("write %x %02X%02X%02X%02X\n", i++, 0,0,0,0);	
+	}
+	fclose(f);
+	return 0;
+}
\ No newline at end of file

testbench/wishbone/lm32_testsys/sw/gpio.h

+#ifndef __GPIO_H
+#define __GPIO_H
+
+#include "inttypes.h"
+
+#include "board.h"
+
+struct GPIO_WB
+{
+  uint32_t CODR;  /*Clear output register*/
+  uint32_t SODR;  /*Set output register*/
+  uint32_t DDR;   /*Data direction register (1 means out)*/
+  uint32_t PSR;   /*Pin state register*/
+};
+
+static volatile struct GPIO_WB *__gpio = (volatile struct GPIO_WB *) BASE_GPIO;
+
+static inline void gpio_out(int pin, int val)
+{
+  if(val)
+    __gpio->SODR = (1<<pin);
+  else
+    __gpio->CODR = (1<<pin);
+}
+
+static inline void gpio_dir(int pin, int val)
+{
+  if(val)
+    __gpio->DDR |= (1<<pin);
+  else
+    __gpio->DDR &= ~(1<<pin);
+}
+
+static inline int gpio_in(int pin)
+{
+  return __gpio->PSR & (1<<pin) ? 1: 0;
+}
+
+        
+#endif
+        

testbench/wishbone/lm32_testsys/sw/inttypes.h

+#ifndef __WRAPPED_INTTYPES_H
+#define __WRAPPED_INTTYPES_H
+
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef signed long long uint64_t;
+
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef signed long long int64_t;
+
+#endif

testbench/wishbone/lm32_testsys/sw/main.c

+#include <stdio.h>
+//#include <stdint.h>
+
+#include "gpio.h"
+
+void _irq_entry(){}
+
+int main(void)
+{
+	uart_init();
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+	uart_write_byte('U');
+
+/*	gpio_dir(1,1);
+	for(;;)
+	{
+		gpio_out(1,0);
+		delay(10);
+		gpio_out(1,1);
+		delay(10);
+	}*/
+}
+
+
+

testbench/wishbone/lm32_testsys/sw/main.ram

+write 0 98000000
+write 1 D0000000
+write 2 D0200000
+write 3 78010000
+write 4 38210000
+write 5 D0E10000
+write 6 F800003A
+write 7 34000000
+write 8 00000000
+write 9 00000000
+write a 00000000
+write b 00000000
+write c 00000000
+write d 00000000
+write e 00000000
+write f 00000000
+write 10 00000000
+write 11 00000000
+write 12 00000000
+write 13 00000000
+write 14 00000000
+write 15 00000000
+write 16 00000000
+write 17 00000000
+write 18 00000000
+write 19 00000000
+write 1a 00000000
+write 1b 00000000
+write 1c 00000000
+write 1d 00000000
+write 1e 00000000
+write 1f 00000000
+write 20 00000000
+write 21 00000000
+write 22 00000000
+write 23 00000000
+write 24 00000000
+write 25 00000000
+write 26 00000000
+write 27 00000000
+write 28 00000000
+write 29 00000000
+write 2a 00000000
+write 2b 00000000
+write 2c 00000000
+write 2d 00000000
+write 2e 00000000
+write 2f 00000000
+write 30 5B9D0000
+write 31 F8000020
+write 32 34010002
+write 33 F8000041
+write 34 E0000030
+write 35 34000000
+write 36 34000000
+write 37 34000000
+write 38 00000000
+write 39 00000000
+write 3a 00000000
+write 3b 00000000
+write 3c 00000000
+write 3d 00000000
+write 3e 00000000
+write 3f 00000000
+write 40 98000000
+write 41 781C0000
+write 42 3B9CFFFC
+write 43 781A0000
+write 44 3B5A8390
+write 45 78010000
+write 46 38210394
+write 47 34020000
+write 48 78030000
+write 49 38630394
+write 4a C8611800
+write 4b F800005F
+write 4c 34010000
+write 4d 34020000
+write 4e 34030000
+write 4f F8000026
+write 50 E0000000
+write 51 379CFFC4
+write 52 5B810004
+write 53 5B820008
+write 54 5B83000C
+write 55 5B840010
+write 56 5B850014
+write 57 5B860018
+write 58 5B87001C
+write 59 5B880020
+write 5a 5B890024
+write 5b 5B8A0028
+write 5c 5B9E0034
+write 5d 5B9F0038
+write 5e 2B81003C
+write 5f 5B810030
+write 60 BB800800
+write 61 3421003C
+write 62 5B81002C
+write 63 C3A00000
+write 64 2B810004
+write 65 2B820008
+write 66 2B83000C
+write 67 2B840010
+write 68 2B850014
+write 69 2B860018
+write 6a 2B87001C
+write 6b 2B880020
+write 6c 2B890024
+write 6d 2B8A0028
+write 6e 2B9D0030
+write 6f 2B9E0034
+write 70 2B9F0038
+write 71 2B9C002C
+write 72 34000000
+write 73 C3C00000
+write 74 C3A00000
+write 75 379CFFFC
+write 76 5B9D0004
+write 77 F8000014
+write 78 34010055
+write 79 F8000017
+write 7a 34010055
+write 7b F8000015
+write 7c 34010055
+write 7d F8000013
+write 7e 34010055
+write 7f F8000011
+write 80 34010055
+write 81 F800000F
+write 82 34010055
+write 83 F800000D
+write 84 34010055
+write 85 F800000B
+write 86 34010055
+write 87 F8000009
+write 88 2B9D0004
+write 89 379C0004
+write 8a C3A00000
+write 8b 78012000
+write 8c 38210100
+write 8d 3402147B
+write 8e 58220004
+write 8f C3A00000
+write 90 379CFFFC
+write 91 5B9D0004
+write 92 78022000
+write 93 202300FF
+write 94 38420100
+write 95 28410000
+write 96 20210001
+write 97 5C20FFFE
+write 98 58430008
+write 99 3401000A
+write 9a 5C610003
+write 9b 3401000D
+write 9c FBFFFFF4
+write 9d 2B9D0004
+write 9e 379C0004
+write 9f C3A00000
+write a0 78012000
+write a1 38210100
+write a2 28210000
+write a3 20210002
+write a4 C3A00000
+write a5 78012000
+write a6 38210100
+write a7 2821000C
+write a8 202100FF
+write a9 C3A00000
+write aa B8204000
+write ab B8202800
+write ac 34010003
+write ad B8602000
+write ae 204900FF
+write af 50230023
+write b0 A1010800
+write b1 44200009
+write b2 212200FF
+write b3 34030000
+write b4 B4A30800
+write b5 30220000
+write b6 34630001
+write b7 5C64FFFD
+write b8 B9000800
+write b9 C3A00000
+write ba 3D210008
+write bb 3403000F
+write bc B8290800
+write bd 3C220010
+write be B9003800
+write bf B8412800
+write c0 B8603000
+write c1 B9000800
+write c2 B8801000
+write c3 54830011
+write c4 34030000
+write c5 34060003
+write c6 B4E31000
+write c7 34630004
+write c8 58450000
+write c9 C8830800
+write ca 5426FFFC
+write cb 3482FFFC
+write cc 00410002
+write cd 20440003
+write ce 34210001
+write cf 3C210002
+write d0 B4E13800
+write d1 B8E02800
+write d2 5C80FFE0
+write d3 E3FFFFE5
+write d4 58250000
+write d5 58250004
+write d6 58250008
+write d7 5825000C
+write d8 3442FFF0
+write d9 34210010
+write da 5446FFFA
+write db 3481FFF0
+write dc 00220004
+write dd 2024000F
+write de 34420001
+write df 3C420004
+write e0 34010003
+write e1 B5023800
+write e2 5481FFE2
+write e3 B8E02800
+write e4 E3FFFFEE
+write e5 E3FFFFEE

testbench/wishbone/lm32_testsys/sw/target/lm32/crt0.S

+/****************************************************************************
+**
+**  Name: crt0ram.S
+**
+**  Description:
+**        Implements boot-code that calls LatticeDDInit (that calls main())
+**        Implements exception handlers (actually, redirectors)
+**
+**  $Revision: $
+**
+** Disclaimer:
+**
+**   This source code is intended as a design reference which
+**   illustrates how these types of functions can be implemented.  It
+**   is the user's responsibility to verify their design for
+**   consistency and functionality through the use of formal
+**   verification methods.  Lattice Semiconductor provides no warranty
+**   regarding the use or functionality of this code.
+**
+** --------------------------------------------------------------------
+**
+**                     Lattice Semiconductor Corporation
+**                     5555 NE Moore Court
+**                     Hillsboro, OR 97214
+**                     U.S.A
+**
+**                     TEL: 1-800-Lattice (USA and Canada)
+**                          (503)268-8001 (other locations)
+**
+**                     web:   http://www.latticesemi.com
+**                     email: techsupport@latticesemi.com
+**
+** --------------------------------------------------------------------------
+**
+**  Change History (Latest changes on top)
+**
+**  Ver    Date        Description
+** --------------------------------------------------------------------------
+**  3.8   Apr-15-2011  Added __MICO_USER_<handler>_HANDLER__ preprocessor to 
+**                     allow customers to implement their own handlers for:
+**                     DATA_ABORT, INST_ABORT
+**  
+**  3.1   Jun-18-2008  Added __MICO_NO_INTERRUPTS__ preprocessor
+**                     option to exclude invoking MicoISRHandler
+**                     to reduce code-size in apps that don't use
+**                     interrupts
+**
+**  3.0   Mar-25-2008  Added Header
+**
+**---------------------------------------------------------------------------
+*****************************************************************************/
+
+/*
+ * LatticeMico32 C startup code.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* From include/sys/signal.h */  
+#define SIGINT  2   /* interrupt */
+#define SIGTRAP 5   /* trace trap */
+#define SIGFPE  8   /* arithmetic exception */
+#define SIGSEGV 11  /* segmentation violation */
+
+//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+
+
+/* Exception handlers - Must be 32 bytes long. */
+        .section    .boot, "ax", @progbits
+	
+        .global	_start  
+_start: 
+	   
+        .global _reset_handler
+        .type 	_reset_handler, @function
+_reset_handler:
+    xor r0, r0, r0
+    wcsr    IE, r0
+    wcsr    IM, r0
+    mvhi    r1, hi(_reset_handler)
+    ori     r1, r1, lo(_reset_handler)
+    wcsr    EBA, r1
+    calli   _crt0
+    nop
+        .size	_reset_handler, .-_reset_handler
+	
+.extern _irq_entry
+.org 0xc0
+        .global _interrupt_handler
+        .type 	_interrupt_handler, @function
+_interrupt_handler:
+    sw      (sp+0), ra
+    calli   _save_all
+    mvi     r1, SIGINT
+#ifndef __MICO_NO_INTERRUPTS__
+    calli  _irq_entry
+#else
+    wcsr    IE, r0
+#endif
+    bi      _restore_all_and_return
+    nop
+    nop
+    nop
+
+.org 0x100
+        .global _crt0
+        .type 	_crt0, @function
+_crt0:
+    /* Clear r0 */
+    xor     r0, r0, r0
+    /* Setup stack and global pointer */
+    mvhi    sp, hi(_fstack)
+    ori     sp, sp, lo(_fstack)
+    mvhi    gp, hi(_gp)
+    ori     gp, gp, lo(_gp)
+	
+    mvhi    r1, hi(_fbss)
+    ori     r1, r1, lo(_fbss)
+    mvi     r2, 0
+    mvhi    r3, hi(_ebss)
+    ori     r3, r3, lo(_ebss)
+    sub     r3, r3, r1
+    calli   memset
+    mvi     r1, 0
+    mvi     r2, 0
+    mvi     r3, 0
+    calli   main
+
+loopf:
+	bi loopf
+
+        .global _save_all
+        .type 	_save_all, @function
+_save_all:
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+    addi    sp, sp, -128
+#else
+    addi    sp, sp, -60
+#endif
+    sw      (sp+4), r1
+    sw      (sp+8), r2
+    sw      (sp+12), r3
+    sw      (sp+16), r4
+    sw      (sp+20), r5
+    sw      (sp+24), r6
+    sw      (sp+28), r7
+    sw      (sp+32), r8
+    sw      (sp+36), r9
+    sw      (sp+40), r10
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+    sw      (sp+44), r11
+    sw      (sp+48), r12
+    sw      (sp+52), r13
+    sw      (sp+56), r14
+    sw      (sp+60), r15
+    sw      (sp+64), r16
+    sw      (sp+68), r17
+    sw      (sp+72), r18
+    sw      (sp+76), r19
+    sw      (sp+80), r20
+    sw      (sp+84), r21
+    sw      (sp+88), r22
+    sw      (sp+92), r23
+    sw      (sp+96), r24
+    sw      (sp+100), r25
+    sw      (sp+104), r26
+    sw      (sp+108), r27
+    sw      (sp+120), ea
+    sw      (sp+124), ba
+    /* ra and sp need special handling, as they have been modified */
+    lw      r1, (sp+128)
+    sw      (sp+116), r1
+    mv      r1, sp
+    addi    r1, r1, 128
+    sw      (sp+112), r1
+#else
+    sw      (sp+52), ea
+    sw      (sp+56), ba
+    /* ra and sp need special handling, as they have been modified */
+    lw      r1, (sp+60)
+    sw      (sp+48), r1
+    mv      r1, sp
+    addi    r1, r1, 60
+    sw      (sp+44), r1
+#endif
+//    xor     r1, r1, r1
+//    wcsr    ie, r1
+    ret
+        .size  	_save_all, .-_save_all
+	
+        .global _restore_all_and_return
+        .type 	_restore_all_and_return, @function
+    /* Restore all registers and return from exception */
+_restore_all_and_return:
+//    addi    r1, r0, 2
+//    wcsr    ie, r1
+    lw      r1, (sp+4)
+    lw      r2, (sp+8) 
+    lw      r3, (sp+12) 
+    lw      r4, (sp+16) 
+    lw      r5, (sp+20) 
+    lw      r6, (sp+24) 
+    lw      r7, (sp+28) 
+    lw      r8, (sp+32) 
+    lw      r9, (sp+36) 
+    lw      r10, (sp+40)
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+    lw      r11, (sp+44)
+    lw      r12, (sp+48)
+    lw      r13, (sp+52)
+    lw      r14, (sp+56)
+    lw      r15, (sp+60)
+    lw      r16, (sp+64)
+    lw      r17, (sp+68)
+    lw      r18, (sp+72)
+    lw      r19, (sp+76)
+    lw      r20, (sp+80)
+    lw      r21, (sp+84)
+    lw      r22, (sp+88)
+    lw      r23, (sp+92)
+    lw      r24, (sp+96)
+    lw      r25, (sp+100)
+    lw      r26, (sp+104)
+    lw      r27, (sp+108)
+    lw      ra, (sp+116)
+    lw      ea, (sp+120)
+    lw      ba, (sp+124)
+    /* Stack pointer must be restored last, in case it has been updated */
+    lw      sp, (sp+112)
+#else
+    lw      ra, (sp+48)
+    lw      ea, (sp+52)
+    lw      ba, (sp+56)
+    /* Stack pointer must be restored last, in case it has been updated */
+    lw      sp, (sp+44)
+#endif
+    nop
+    eret
+        .size   _restore_all_and_return, .-_restore_all_and_return
+

testbench/wishbone/lm32_testsys/sw/target/lm32/irq.c

+#include "irq.h"
+
+void disable_irq()
+{
+    unsigned int ie, im;
+    unsigned int Mask = ~1;
+
+    /* disable peripheral interrupts in case they were enabled */
+    asm volatile ("rcsr %0,ie":"=r"(ie));
+    ie &= (~0x1);
+    asm volatile ("wcsr ie, %0"::"r"(ie));
+
+    /* disable mask-bit in im */
+    asm volatile ("rcsr %0, im":"=r"(im));
+    im &= Mask;
+    asm volatile ("wcsr im, %0"::"r"(im));
+
+}
+
+
+void enable_irq()
+{
+    unsigned int ie, im;
+    unsigned int Mask = 1;
+
+
+    /* disable peripheral interrupts in-case they were enabled*/
+    asm volatile ("rcsr %0,ie":"=r"(ie));
+    ie &= (~0x1);
+    asm volatile ("wcsr ie, %0"::"r"(ie));
+
+    /* enable mask-bit in im */
+    asm volatile ("rcsr %0, im":"=r"(im));
+    im |= Mask;
+    asm volatile ("wcsr im, %0"::"r"(im));
+
+    ie |= 0x1;
+    asm volatile ("wcsr ie, %0"::"r"(ie));
+}

testbench/wishbone/lm32_testsys/sw/target/lm32/ram.ld

+/*
+ * Simulator Link script for Lattice Mico32.
+ * Contributed by Jon Beniston <jon@beniston.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf32-lm32")
+ENTRY(_start)
+/*INPUT() */
+GROUP(-lgcc -lc)
+
+MEMORY
+{
+    ram : ORIGIN = 0x00000000, LENGTH = 0x10000
+}
+
+SECTIONS
+{
+
+  .boot : { *(.boot) } > ram
+   
+  /* Code */
+  .text           :
+  {
+    . = ALIGN(4);
+    _ftext = .;
+    _ftext_rom = LOADADDR(.text);
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    *(.gnu.warning)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    /* Constructors and destructors */
+    KEEP (*crtbegin*.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    KEEP (*(.jcr))
+    _etext = .;
+  } > ram =0 
+
+  /* Exception handlers */
+  .eh_frame_hdr : { *(.eh_frame_hdr) } > ram
+  .eh_frame : { KEEP (*(.eh_frame)) } > ram
+  .gcc_except_table : { *(.gcc_except_table) *(.gcc_except_table.*) } > ram
+    
+  /* Read-only data */
+  .rodata         : 
+  { 
+    . = ALIGN(4);
+    _frodata = .;
+    _frodata_rom = LOADADDR(.rodata);
+    *(.rodata .rodata.* .gnu.linkonce.r.*) 
+    *(.rodata1)
+    _erodata = .;
+  } > ram
+        
+  /* Data */
+  .data           : 
+  {
+    . = ALIGN(4);
+    _fdata = .;
+    _fdata_rom = LOADADDR(.data);
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.data1)
+    SORT(CONSTRUCTORS)
+    _gp = ALIGN(16) + 0x7ff0;
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    _edata = .;
+  } > ram 
+  
+  /* BSS */
+  .bss           :
+  {
+    . = ALIGN(4);
+    _fbss = .;
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+    _end = .;
+    PROVIDE (end = .);
+  } > ram
+  
+  /* First location in stack is highest address in RAM */
+  PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
+  
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+}

testbench/wishbone/lm32_testsys/sw/uart.c

+#include "inttypes.h"
+#include "uart.h"
+
+#define CPU_CLOCK 1000000
+#define UART_BAUDRATE 10000
+#define BASE_UART 0x20000100
+
+#include "wb_uart.h"
+
+#define CALC_BAUD(baudrate) (((((unsigned long long)baudrate*8ULL)<<(16-7))+(CPU_CLOCK>>8))/(CPU_CLOCK>>7))
+ 
+static volatile struct UART_WB *uart = (volatile struct UART_WB *) BASE_UART;
+
+void uart_init()
+{
+	uart->BCR = CALC_BAUD(UART_BAUDRATE);
+}
+
+void uart_write_byte(unsigned char x)
+{
+	while( uart->SR & UART_SR_TX_BUSY);
+
+	uart->TDR = x;
+	if(x == '\n')
+		uart_write_byte('\r');
+}
+
+int uart_poll()
+{
+ 	return uart->SR & UART_SR_RX_RDY;
+}
+
+int uart_read_byte()
+{
+ 	return uart ->RDR & 0xff;
+}
\ No newline at end of file

testbench/wishbone/lm32_testsys/sw/uart.h

+#ifndef __UART_H
+#define __UART_H
+
+int mprintf(char const *format, ...);
+
+void uart_init();
+void uart_write_byte(unsigned char x);
+  
+#endif

testbench/wishbone/lm32_testsys/sw/wb_uart.h

+/*
+  Register definitions for slave core: Simple Wishbone UART
+
+  * File           : wb_uart.h
+  * Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+  * Created        : Tue Oct  4 18:46:41 2011
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
+#define __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Status Register */
+
+/* definitions for field: TX busy in reg: Status Register */
+#define UART_SR_TX_BUSY                       WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: RX ready in reg: Status Register */
+#define UART_SR_RX_RDY                        WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Baudrate control register */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for field: Transmit data in reg: Transmit data regsiter */
+#define UART_TDR_TX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_TDR_TX_DATA_SHIFT                0
+#define UART_TDR_TX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_TDR_TX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for field: Received data in reg: Receive data regsiter */
+#define UART_RDR_RX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_RDR_RX_DATA_SHIFT                0
+#define UART_RDR_RX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_RDR_RX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Host VUART Tx register */
+
+/* definitions for field: TX Data in reg: Host VUART Tx register */
+#define UART_HOST_TDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
+#define UART_HOST_TDR_DATA_SHIFT              0
+#define UART_HOST_TDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_HOST_TDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: TX Ready in reg: Host VUART Tx register */
+#define UART_HOST_TDR_RDY                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for register: Host VUART Rx register */
+
+/* definitions for field: RX Data in reg: Host VUART Rx register */
+#define UART_HOST_RDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
+#define UART_HOST_RDR_DATA_SHIFT              0
+#define UART_HOST_RDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_HOST_RDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: RX Ready in reg: Host VUART Rx register */
+#define UART_HOST_RDR_RDY                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: RX FIFO Count in reg: Host VUART Rx register */
+#define UART_HOST_RDR_COUNT_MASK              WBGEN2_GEN_MASK(9, 16)
+#define UART_HOST_RDR_COUNT_SHIFT             9
+#define UART_HOST_RDR_COUNT_W(value)          WBGEN2_GEN_WRITE(value, 9, 16)
+#define UART_HOST_RDR_COUNT_R(reg)            WBGEN2_GEN_READ(reg, 9, 16)
+
+PACKED struct UART_WB {
+  /* [0x0]: REG Status Register */
+  uint32_t SR;
+  /* [0x4]: REG Baudrate control register */
+  uint32_t BCR;
+  /* [0x8]: REG Transmit data regsiter */
+  uint32_t TDR;
+  /* [0xc]: REG Receive data regsiter */
+  uint32_t RDR;
+  /* [0x10]: REG Host VUART Tx register */
+  uint32_t HOST_TDR;
+  /* [0x14]: REG Host VUART Rx register */
+  uint32_t HOST_RDR;
+};
+
+#endif

testbench/wishbone/lm32_testsys/sw/wb_vuart.h

+/*
+  Register definitions for slave core: Simple Wishbone UART
+
+  * File           : wb_uart.h
+  * Author         : auto-generated by wbgen2 from uart.wb
+  * Created        : Mon Jul 18 01:19:24 2011
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_UART_WB
+#define __WBGEN2_REGDEFS_UART_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Status Register */
+
+/* definitions for field: TX busy in reg: Status Register */
+#define UART_SR_TX_BUSY                       WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: RX ready in reg: Status Register */
+#define UART_SR_RX_RDY                        WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Baudrate control register */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for field: Transmit data in reg: Transmit data regsiter */
+#define UART_TDR_TX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_TDR_TX_DATA_SHIFT                0
+#define UART_TDR_TX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_TDR_TX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for field: Received data in reg: Receive data regsiter */
+#define UART_RDR_RX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_RDR_RX_DATA_SHIFT                0
+#define UART_RDR_RX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_RDR_RX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+/* [0x0]: REG Status Register */
+#define UART_REG_SR 0x00000000
+/* [0x4]: REG Baudrate control register */
+#define UART_REG_BCR 0x00000004
+/* [0x8]: REG Transmit data regsiter */
+#define UART_REG_TDR 0x00000008
+/* [0xc]: REG Receive data regsiter */
+#define UART_REG_RDR 0x0000000c
+#endif

testbench/wishbone/lm32_testsys/wave.do

+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/U_Intercon/g_num_masters
+add wave -noupdate /main/DUT/U_Intercon/g_num_slaves
+add wave -noupdate /main/DUT/U_Intercon/g_registered
+add wave -noupdate /main/DUT/U_Intercon/clk_sys_i
+add wave -noupdate /main/DUT/U_Intercon/rst_n_i
+add wave -noupdate /main/DUT/U_Intercon/slave_i
+add wave -noupdate /main/DUT/U_Intercon/slave_o
+add wave -noupdate /main/DUT/U_Intercon/master_i
+add wave -noupdate /main/DUT/U_Intercon/master_o
+add wave -noupdate /main/DUT/U_Intercon/cfg_address_i
+add wave -noupdate /main/DUT/U_Intercon/cfg_mask_i
+add wave -noupdate /main/DUT/U_Intercon/previous
+add wave -noupdate /main/DUT/U_Intercon/granted
+add wave -noupdate /main/DUT/U_Intercon/issue
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {4093545 ps} 0}
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {3879920 ps} {4290080 ps}