virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1

modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd

@@ -110,7 +110,7 @@ begin  -- syn
 
   srst <= not rst_n_i;
 
-  srstreg <= '0' when g_dual_clock = true else srst;
+  srstreg <= '0';
   
   gen_fifo36 : if(m.is_36 and m.d_width > 0) generate
     assert false report "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." severity note;