diff --git a/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd b/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
index edba9c9079ad262dcbf956533a4ba9509149a813..fb269f1b1d7afbd6d50f4869a368fa6b25f14201 100644
--- a/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
+++ b/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
@@ -110,7 +110,7 @@ begin  -- syn
 
   srst <= not rst_n_i;
 
-  srstreg <= '0' when g_dual_clock = true else srst;
+  srstreg <= '0';
   
   gen_fifo36 : if(m.is_36 and m.d_width > 0) generate
     assert false report "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." severity note;