From 17d08e592c482848bf1ce9401f39a2a8749d04f4 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Wed, 8 May 2019 16:48:48 +0200
Subject: [PATCH] virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is
TRUE and DO_REG is 1
---
modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd b/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
index edba9c90..fb269f1b 100644
--- a/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
+++ b/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
@@ -110,7 +110,7 @@ begin -- syn
srst <= not rst_n_i;
- srstreg <= '0' when g_dual_clock = true else srst;
+ srstreg <= '0';
gen_fifo36 : if(m.is_36 and m.d_width > 0) generate
assert false report "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." severity note;
--
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