Driver developers information
Memory map
Fine Delay Core internals
This is the mapping of the internal FD core components with respect to the core's base address
Wishbone Cores | ||||
---|---|---|---|---|
* Offset (bytes) * | Description | Peripherals | Internal mapping | Status |
0x000 | Main Registers | FD Core shared control registers (TDC and global configuration) | wbgen2 doc | Available |
0x100 | Channel 1 Registers | FD Core output channel 1 control registers (delay/pulse gen settings) | wbgen2 doc | Available |
0x200 | Channel 2 Registers | FD Core output channel 2 control registers (delay/pulse gen settings) | wbgen2 doc | Available |
0x300 | Channel 3 Registers | FD Core output channel 3 control registers (delay/pulse gen settings) | wbgen2 doc | Available |
0x400 | Channel 4 Registers | FD Core output channel 4 control registers (delay/pulse gen settings) | wbgen2 doc | Available |
0x500 | FMC 1-wire master | Thermometer + unique ID (on the respective FMC) | registers | Available |