Changelog 05052011

Changes between V1 and V2:

Top level schematic:

Clock_generator.SchDoc:

replaced IVT3200 oscillator with 25 MHz VM53 oscillator as in the SPEC card
AC-coupled OSC1 oscillator output to the PLL (C80)
removed TDC_STOP outputs, added (125 / 16) MHz TDC_START output (LVPECL)
new assignment of the outputs of AD9516:
-> OUT0-OUT3: 125 MHz (flip-flop clocks)
-> OUT4-OUT5: 7.8125 MHz (125 MHz / 16): TDC start (and a copy for the FPGA)
-> OUT7A: 31.25 MHz (125 MHz / 4): TDC ref clock
-> OUT8: 125 MHz LVDS (FPGA reference clock)
removed coupling capacitors on CLK125 diff line (LVDS)

FMC_Connector.SchDoc:

LED_MEM.SchDoc:

replaced MCP9801 sensor with Dallas's 1-wire sensor (DS18B20U+). The sensor is placed directly under one of the delay chips and is a
part of tempereature compensation loop

TDC.SchDoc:

reconfigured the TDC inputs: DStart is a 7.8125 MHz clock and DStop1 is the trigger input
removed DStop2 input
Y-type termination for LVPECL lines (works better with coupled lines and draws less current)
redesigned decoupling and regulators, used the same components as in ACAM's devkit. Replaced SOT-223 1117's with SOT-89 version (smaller footprint)
added another linear regularor (IC6) for clean TDC digital supply (VDDQ_TDC).
removed IrFlag and LoadFlag lines
wired Alutrigger to the FMC connector (for forced purge of TDC FIFO)
decoupling caps for the TDC as in the app note and ACAM's reference design

Channel_Delay.SchDoc:

removed 50 ohm terminations on D inputs of the flip-flops (they accept LVTTL levels)
changed the mode of D/LEN inputs in IC2, IC7 to LVTTL (added a 2.2k resistor between Vcf pin and GND)
Y-type LVPECL terminations wherever possible
replaced the delay chips with SY89295UMG (or MC100EP195BMNG - parts are interchangeable) for improved thermal performance (MLF packages)

Layout: