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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Last edited by
Jan 19, 2011
replaced IC1 (was: MC100EPT23DTG, TSSOP) with MC100EPT23DG (SO-8 package) due to problems with availability.
replaced IC3 (was: MC100LVEL29DG, SOIC16) with MC100EP29DTG (TSSOP) due to problems with availability, PCB space constraints and lack of VBB bias output.
replaced output buffer (IC11) with SN64BCT25244DW (the same as in CTRV/CTRP - single channel can drive 50 ohm load)
replaced IC18 (MC100EPT21 - calibration buffer) with MC100EPT23DG to reduce the number of different components in the design
replaced serial termination resistors next to the TDC with 8x resistor ladders due to space reasons
delay chain flip flops now use VBB to bias data inputs
routed individual LVPECL clocks to each output stage flip flop (with length matching) to reduce the load and avoid termination/biasing problems
LVDS clock to the FPGA (CLK_M2C) is now AC-coupled, as the PLL Vdd is 3.3 V and the IOB Vdd on the carrier is 1.8 V
added 100 nF decoupling capacitor for each input stage IC
PLL reset re-wired to RESETn (it's active 0, CERN libary components don't have dashes over inverted pins with default Altium settings)
reordered outputs in AD9516 PLL to improve routing
transition from 4 layers -> 6 layers (was necessary for diff pair routing with length matching and to avoid any signals crossing power planes)
added guard ring (BYPASS) around the PLL filter
moved the voltage reference closer to the PLL
added thermal via patterns under AD9516 (dissipates a lot of heat)
added OHWR/CERN notice on the silkscreen
fixed mounting holes connections
updated stackup information (standard 1.55mm thickness, 18/35/35/35/35/18 um copper, 0.2/0.36/0.36/0.36/0.2 mm buildup).
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