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FMC DEL 1ns 4cha
Commit ecd0bb00 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'tom-spec-convention' into proposed_master

parents eca0894f 32f77963
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.gitmodules
View file @ ecd0bb00
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
doc/design-notes/fd_main_regs.in
View file @ ecd0bb00
......@@ -125,19 +125,27 @@ Timestamp Buffer Debug Values Register
REG @tab
@code{TSBR_ADVANCE} @tab
Timestamp Buffer Advance Register
@item @code{0x7c} @tab
REG @tab
@code{FMC_SLOT_ID} @tab
FMC Slot ID Register
@item @code{0x80} @tab
REG @tab
@code{IODELAY_ADJ} @tab
I/O Delay Adjust Register
@item @code{0xa0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x84} @tab
@item @code{0xa4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x88} @tab
@item @code{0xa8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0x8c} @tab
@item @code{0xac} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
......@@ -354,6 +362,11 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +378,7 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......@@ -791,6 +805,26 @@ Debug value
@tab @code{0} @tab
Advance buffer readout
@end multitable
@regsection @code{FMC_SLOT_ID} - FMC Slot ID Register
Index of the hardware FMC slot the card is in.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{SLOT_ID}
@tab @code{X} @tab
Slot ID
@end multitable
@regsection @code{IODELAY_ADJ} - I/O Delay Adjust Register
Setup time adjust for certain signals (e.g. TDC_START).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{5...0}
@tab R/W @tab
@code{N_TAPS}
@tab @code{X} @tab
Number of delay line taps.
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
......
hdl/include/jittery_delay.svh
View file @ ecd0bb00
`timescale 10fs/10fs
module jittery_delay
(
......@@ -20,4 +21,4 @@ module jittery_delay
out_o <= #(delta) in_i;
end
endmodule // jittery_delay
\ No newline at end of file
endmodule // jittery_delay
hdl/include/regs/fd_main_regs.vh
View file @ ecd0bb00
......@@ -53,6 +53,8 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......@@ -155,28 +157,34 @@
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define ADDR_FD_FMC_SLOT_ID 8'h7c
`define FD_FMC_SLOT_ID_SLOT_ID_OFFSET 0
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IER 8'h84
`define ADDR_FD_EIC_IER 8'ha4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
`define FD_EIC_IER_DMTD_SPLL 32'h00000002
`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
`define FD_EIC_IER_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IMR 8'h88
`define ADDR_FD_EIC_IMR 8'ha8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_ISR 8'h8c
`define ADDR_FD_EIC_ISR 8'hac
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
......
hdl/include/tunable_clock_gen.svh
View file @ ecd0bb00
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......@@ -74,4 +74,4 @@ module tunable_clock_gen
end // else: !if(enable)
assign clk_o = clk;
endmodule // tunable_clock_gen
\ No newline at end of file
endmodule // tunable_clock_gen
hdl/include/vme64x_bfm/svec_vme_buffers.svh
View file @ ecd0bb00
......@@ -162,6 +162,16 @@ function automatic bit[5:0] _gen_ga(int slot);
return {^slot_id, ~slot_id};
endfunction // _gen_ga
function automatic bit[4:0] _gen_ga_convention(int slot);
bit[4:0] slot_id = slot;
return {~slot_id};
endfunction // _gen_ga
function automatic bit _gen_gap_convention(int slot);
bit[4:0] slot_id = slot;
return ^slot_id;
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
......@@ -190,4 +200,30 @@ endfunction // _gen_ga
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
`define WIRE_VME_PINS_CONVENTION(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_SYSRESET_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga_convention(slot_id)),\
.VME_GAP_i(_gen_gap_convention(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
ddr3-sp6-core @ 1a129390
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ 4f414ece
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
Subproject commit 4f414ececa8286f49bc6324425a00b9561884375
gn4124-core @ 91d5efac
Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 7911a138
Subproject commit 7911a1387bd47bc74e52957509ba7f303b5880b8
svec @ 41415b81
Subproject commit 41415b8141e5466248e55eadd30ba4a68e4b3e21
vme64x-core @ 366ca4db
Subproject commit 633d31749b104d4ca04c569cf3e30c5a6c9902b5
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
wr-cores @ ad01cd09
Subproject commit c466a66b4d17173d3ee5e18af26a2d263a760aa0
Subproject commit ad01cd0965381808974decabd924c02ce902a3cc
hdl/rtl/fd_acam_timestamper.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-07-02
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -423,21 +423,10 @@ begin -- behave
-- Input: tdc_start_i
-- Output: tdc_start_d
--
-- A synchronizer chain for detecting the relation between clk_tdc_i
-- and clk_ref_i. Since both clocks are almost in phase, the first stage
-- reacts to the falling edge of the reference clock to satisfy setup/hold
-- requirements.
--
p_sync_tdclk_fedge : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
end if;
end process;
p_sync_tdclk_redge : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
tdc_start_d(1) <= tdc_start_d(0);
tdc_start_d(2) <= tdc_start_d(1);
end if;
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ ecd0bb00
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -22,93 +22,119 @@ package fd_channel_wbgen2_pkg is
type t_fd_channel_in_registers is record
dcr_pg_trig_i : std_logic;
dcr_upd_done_i : std_logic;
end record;
end record;
constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
dcr_pg_trig_i => '0',
dcr_upd_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ ecd0bb00
This diff is collapsed.
hdl/rtl/fd_delay_channel_driver.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-07-18
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ ecd0bb00
This diff is collapsed.
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ ecd0bb00
This diff is collapsed.
hdl/rtl/fd_main_wishbone_slave.wb
View file @ ecd0bb00
......@@ -404,7 +404,17 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
};
reg {
prefix = "CALR";
......@@ -1031,7 +1041,37 @@ peripheral {
};
};
reg {
name = "FMC Slot ID Register";
description = "Index of the hardware FMC slot the card is in.";
prefix = "FMC_SLOT_ID";
field {
name = "Slot ID";
prefix = "SLOT_ID";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I/O Delay Adjust Register";
description = "Setup time adjust for certain signals (e.g. TDC_START).";
prefix = "IODELAY_ADJ";
field {
name = "Number of delay line taps.";
prefix = "N_TAPS";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
irq {
name = "Timestamp Buffer interrupt.";
description = "Triggers when there are timestamps in the readout buffer";
......
hdl/rtl/fine_delay_core.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-08-03
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -65,7 +65,11 @@ entity fine_delay_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
g_with_debug_output : boolean := false;
-- index of the slot the core is assigned to, written to
-- FMC_SLOT_ID register
g_fmc_slot_id : integer := 0
);
port (
......@@ -195,7 +199,7 @@ entity fine_delay_core is
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Misc signals: I2C EEPROM, FMC presence
-- Misc signals: I2C EEPROM, FMC presence, I/O calibration
---------------------------------------------------------------------------
i2c_scl_o : out std_logic;
......@@ -207,6 +211,11 @@ entity fine_delay_core is
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone slave (classic/pipelined)
......@@ -358,6 +367,12 @@ architecture rtl of fine_delay_core is
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
signal iodelay_ntaps : std_logic_vector(5 downto 0);
signal iodelay_cnt : unsigned(5 downto 0);
signal iodelay_div : unsigned(4 downto 0);
signal iodelay_tick : std_logic;
signal iodelay_cal_done : std_logic;
begin -- rtl
U_WB_Adapter : wb_slave_adapter
......@@ -504,6 +519,8 @@ begin -- rtl
);
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
......@@ -554,12 +571,12 @@ begin -- rtl
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_0_i,
clk_in_i => clk_ref_0_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys,
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
process(clk_ref_0_i)
begin
......@@ -633,12 +650,12 @@ begin -- rtl
U_Sync_Valid_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys,
clk_out_i => clk_ref_0_i,
clk_out_i => clk_ref_0_i,
rst_out_n_i => rst_n_ref,
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
process(clk_sys_i)
begin
......@@ -780,6 +797,7 @@ begin -- rtl
regs_towb_local.gcr_ddr_locked_i <= pll_status_i;
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
......@@ -839,5 +857,62 @@ begin -- rtl
gen_without_dbg_out : if(not g_with_debug_output) generate
dbg_o <= (others => '0');
end generate gen_without_dbg_out;
p_handle_iodelay: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys = '0' then
idelay_cal_o <= '0';
idelay_inc_o <= '1';
idelay_rst_o <= '0';
idelay_ce_o <= '0';
iodelay_cal_done <= '0';
iodelay_cnt <= (others => '0');
iodelay_div <= (others => '0');
iodelay_tick <= '0';
else
if iodelay_cal_done = '0' then
idelay_cal_o <= '1';
iodelay_cnt <= iodelay_cnt + 1;
if iodelay_cnt = 15 then
iodelay_cnt <= (others => '0');
iodelay_cal_done <= '1';
end if;
else
idelay_cal_o <= '0';
end if;
iodelay_div <= iodelay_div + 1;
if iodelay_div = 0 then
iodelay_tick <= '1';
else
iodelay_tick <= '0';
end if;
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_cnt <= unsigned(regs_fromwb.iodelay_adj_n_taps_o);
idelay_rst_o <= '1';
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
else
idelay_rst_o <= '0';
end if;
if iodelay_cal_done = '1' and iodelay_tick = '1' and iodelay_cnt /= 0 then
idelay_ce_o <= '1';
iodelay_cnt <= iodelay_cnt - 1;
else
idelay_ce_o <= '0';
end if;
end if;
end if;
end process;
regs_towb_local.iodelay_adj_n_taps_i <= iodelay_ntaps;
end rtl;
hdl/rtl/fine_delay_pkg.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2019-10-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -237,32 +237,6 @@ package fine_delay_pkg is
regs_o : out t_fd_channel_out_registers);
end component;
component fd_main_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers);
end component;
component fd_delay_line_arbiter
port (
......@@ -382,7 +356,8 @@ package fine_delay_pkg is
g_simulation : boolean := false;
g_with_direct_timestamp_io : boolean := false;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
g_address_granularity : t_wishbone_address_granularity;
g_fmc_slot_id : integer := 0);
port (
clk_ref_0_i : in std_logic;
clk_ref_180_i : in std_logic;
......@@ -436,6 +411,10 @@ package fine_delay_pkg is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
......
hdl/syn/spec/Manifest.py
View file @ ecd0bb00
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_fine_delay_top.xise"
syn_tool = "ise"
syn_top = "spec_fine_delay_top"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
syn_tool = "ise"
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
modules = { "local" : [ "../../top/spec", "../../platform" ] }
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/spec/spec_fine_delay.xise deleted 100644 → 0
View file @ eca0894f
This diff is collapsed.
hdl/syn/svec/Manifest.py
View file @ ecd0bb00
board = "svec"
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_tool = "ise"
svec_base_ucf = ['wr', 'led', 'gpio']
files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../top/svec", "../../platform" ] }
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/svec/svec_fine_delay.xise
View file @ ecd0bb00
This diff is collapsed.
hdl/syn/svec/wrc-release.ram deleted 100644 → 0
View file @ eca0894f
This diff is collapsed.
hdl/testbench/svec_wr_top/Manifest.py
View file @ ecd0bb00
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
include_dirs = ["../../include/vme64x_bfm",
"../../include/wb", "../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
files = [ "main.sv" ]
modules = { "local" : [ "../../top/svec" ] }
modules = {"local": ["../../top/svec" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
#except:
# pass
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ ecd0bb00
......@@ -223,34 +223,34 @@ module fdelay_board (
endmodule // main
`define WIRE_FINE_DELAY_PINS(fmc_index,iface) \
.fd``fmc_index``_tdc_start_p_i (iface.core.tdc_start_p), \
.fd``fmc_index``_tdc_start_n_i (iface.core.tdc_start_n), \
.fd``fmc_index``_clk_ref_p_i (iface.core.clk_ref_p), \
.fd``fmc_index``_clk_ref_n_i (iface.core.clk_ref_n), \
.fd``fmc_index``_trig_a_i (iface.core.trig_a), \
.fd``fmc_index``_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fd``fmc_index``_tdc_d_b (iface.core.tdc_d), \
.fd``fmc_index``_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fd``fmc_index``_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fd``fmc_index``_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fd``fmc_index``_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fd``fmc_index``_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fd``fmc_index``_led_trig_o (iface.core.led_trig), \
.fd``fmc_index``_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fd``fmc_index``_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fd``fmc_index``_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fd``fmc_index``_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fd``fmc_index``_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fd``fmc_index``_spi_sclk_o (iface.core.spi_sclk), \
.fd``fmc_index``_spi_mosi_o (iface.core.spi_mosi), \
.fd``fmc_index``_spi_miso_i (iface.core.spi_miso), \
.fd``fmc_index``_delay_len_o (iface.core.delay_len), \
.fd``fmc_index``_delay_val_o (iface.core.delay_val), \
.fd``fmc_index``_delay_pulse_o (iface.core.delay_pulse), \
.fd``fmc_index``_dmtd_clk_o (iface.core.dmtd_clk), \
.fd``fmc_index``_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fd``fmc_index``_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fd``fmc_index``_pll_status_i (iface.core.pll_status), \
.fd``fmc_index``_ext_rst_n_o (iface.core.ext_rst_n), \
.fd``fmc_index``_onewire_b (iface.core.onewire)
.fmc``fmc_index``_fd_tdc_start_p_i (iface.core.tdc_start_p), \
.fmc``fmc_index``_fd_tdc_start_n_i (iface.core.tdc_start_n), \
.fmc``fmc_index``_fd_clk_ref_p_i (iface.core.clk_ref_p), \
.fmc``fmc_index``_fd_clk_ref_n_i (iface.core.clk_ref_n), \
.fmc``fmc_index``_fd_trig_a_i (iface.core.trig_a), \
.fmc``fmc_index``_fd_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fmc``fmc_index``_fd_tdc_d_b (iface.core.tdc_d), \
.fmc``fmc_index``_fd_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fmc``fmc_index``_fd_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fmc``fmc_index``_fd_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fmc``fmc_index``_fd_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fmc``fmc_index``_fd_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fmc``fmc_index``_fd_led_trig_o (iface.core.led_trig), \
.fmc``fmc_index``_fd_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fmc``fmc_index``_fd_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fmc``fmc_index``_fd_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fmc``fmc_index``_fd_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fmc``fmc_index``_fd_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fmc``fmc_index``_fd_spi_sclk_o (iface.core.spi_sclk), \
.fmc``fmc_index``_fd_spi_mosi_o (iface.core.spi_mosi), \
.fmc``fmc_index``_fd_spi_miso_i (iface.core.spi_miso), \
.fmc``fmc_index``_fd_delay_len_o (iface.core.delay_len), \
.fmc``fmc_index``_fd_delay_val_o (iface.core.delay_val), \
.fmc``fmc_index``_fd_delay_pulse_o (iface.core.delay_pulse), \
.fmc``fmc_index``_fd_dmtd_clk_o (iface.core.dmtd_clk), \
.fmc``fmc_index``_fd_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fmc``fmc_index``_fd_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fmc``fmc_index``_fd_pll_status_i (iface.core.pll_status), \
.fmc``fmc_index``_fd_ext_rst_n_o (iface.core.ext_rst_n), \
.fmc``fmc_index``_fd_onewire_b (iface.core.onewire)
hdl/testbench/svec_wr_top/main.sv
View file @ ecd0bb00
......@@ -105,7 +105,6 @@ module main;
`DECLARE_VME_BUFFERS(VME.slave);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
......@@ -116,7 +115,7 @@ module main;
.rst_n_i(rst_n),
`WIRE_VME_PINS(8),
`WIRE_VME_PINS_CONVENTION(8),
`WIRE_FINE_DELAY_PINS(0, I_fmc0),
`WIRE_FINE_DELAY_PINS(1, I_fmc1)
);
......@@ -169,6 +168,7 @@ module main;
Timestamp dly, t_start;
CSimDrv_FineDelay drv0;
CSimDrv_FineDelay drv1;
uint64_t d;
#20us;
......@@ -181,15 +181,19 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv1 = new(acc, 'h80020000);
drv1.init();
t_start=new;
drv0.set_idelay_taps(5);
/* t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
drv0.config_output(1, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001100, -1);
drv0.config_output(2, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001200, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1); */
$display("Init done");
......
hdl/testbench/svec_wr_top/run.do
View file @ ecd0bb00
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
vsim work.main -voptargs=+acc
vsim -t 1ps work.main -novopt -L unisim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ ecd0bb00
......@@ -39,6 +39,17 @@ class CSimDrv_FineDelay;
endfunction // new
task set_idelay_taps( int taps );
uint64_t tdcsr;
$display("Set Idelay taps : %d\n", taps);
writel(`ADDR_FD_IODELAY_ADJ, taps);
endtask // set_idelay_taps
/* fixme - maybe use real mcp23s17 model instead of this stub? */
task sgpio_write(int value);
......
hdl/testbench/svec_wr_top/wave.do
View file @ ecd0bb00
This diff is collapsed.
hdl/top/spec/Manifest.py
View file @ ecd0bb00
files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
files = ["spec_fine_delay_top.vhd", "spec_fine_delay_top.ucf"]
fetchto = "../../ip_cores"
modules = {
"local" : [
"../../rtl",
"../../platform",
],
"git" : [
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
"../../rtl",
"../../platform",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/gn4124-core",
"../../ip_cores/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_fine_delay_top.ucf 0 → 100644
View file @ ecd0bb00
####################################################################################
# FineDelay V3/V4 pins
####################################################################################
NET "fmc0_fd_clk_ref_n_i" LOC = L22 ;
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_clk_ref_p_i" LOC = L20 ;
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_delay_len_o[3]" LOC = W14 ;
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = Y14 ;
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = Y18 ;
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = W17 ;
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = W13 ;
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[2]" LOC = V13 ;
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[1]" LOC = U15 ;
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[0]" LOC = T15 ;
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" LOC = A20 ;
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = B20 ;
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[2]" LOC = A19 ;
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[3]" LOC = C19 ;
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = W18 ;
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = V17 ;
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = C18 ;
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = D17 ;
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = W15 ;
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = Y16 ;
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_led_trig_o" LOC = V11 ;
NET "fmc0_fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_miso_i" LOC = AB18 ;
NET "fmc0_fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_mosi_o" LOC = AA18 ;
NET "fmc0_fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_sclk_o" LOC = Y17 ;
NET "fmc0_fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_clk_o" LOC = T12 ;
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_out_i" LOC = U12 ;
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_pll_status_i" LOC = AB15 ;
NET "fmc0_fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_alutrigger_o" LOC = W12 ;
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_ext_rst_n_o" LOC = T11 ;
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[0]" LOC = AB12 ;
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[1]" LOC = U8 ;
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[10]" LOC = R9 ;
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[11]" LOC = R8 ;
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[12]" LOC = AA6 ;
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[13]" LOC = AB6 ;
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[14]" LOC = U9 ;
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[15]" LOC = V9 ;
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[16]" LOC = Y7 ;
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[17]" LOC = AB7 ;
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[18]" LOC = AA8 ;
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[19]" LOC = AB8 ;
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[2]" LOC = AA12 ;
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[20]" LOC = T10 ;
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[21]" LOC = U10 ;
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[22]" LOC = W10 ;
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[23]" LOC = Y10 ;
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[24]" LOC = Y9 ;
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[25]" LOC = AB9 ;
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[26]" LOC = AA4 ;
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[27]" LOC = AB4 ;
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[3]" LOC = T8 ;
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[4]" LOC = W8 ;
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[5]" LOC = V7 ;
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[6]" LOC = Y6 ;
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[7]" LOC = W6 ;
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[8]" LOC = Y5 ;
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[9]" LOC = AB5 ;
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_emptyf_i" LOC = Y12 ;
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_oe_n_o" LOC = AA16 ;
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_rd_n_o" LOC = AB13 ;
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_dis_o" LOC = R13 ;
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_n_i" LOC = F16 ;
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_start_p_i" LOC = E16 ;
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_stop_dis_o" LOC = T14 ;
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_wr_n_o" LOC = Y13 ;
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_trig_a_i" LOC = Y11 ;
NET "fmc0_fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_onewire_b" LOC = W11 ;
NET "fmc0_fd_onewire_b" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc0_fd_clk_ref_p_i" TNM_NET = fmc0_fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fmc0_fd_clk_ref_p_i" 8 ns HIGH 50%;
PIN "cmp0_fd_ddr_pll/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "cmp0_fd_ddr_pll/pll_base_inst/CLKOUT0" TNM_NET="fmc0_dcm_clk_ref_0";
TIMESPEC TS_crossdomain_4 = FROM "clk_sys_62m5" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "fmc0_dcm_clk_ref_0" TO "clk_sys_62m5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_9 = FROM "clk_ref_125m" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
hdl/top/spec/spec_fine_delay_top.vhd 0 → 100644
View file @ ecd0bb00
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hdl/top/spec/spec_reset_gen.vhd deleted 100644 → 0
View file @ eca0894f
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/spec_top.ucf deleted 100644 → 0
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hdl/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ eca0894f
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "7dd0a8c348dee0a3a660143c80487a8a",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
hdl/top/svec/Manifest.py
View file @ ecd0bb00
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "bicolor_led_ctrl.vhd", "bicolor_led_ctrl_pkg.vhd" ]
files = ["svec_fine_delay_top.vhd", "svec_fine_delay_top.ucf"]
fetchto = "../../ip_cores"
modules = {
"local" : [
"../../rtl",
"../../platform",
],
"git" : [
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
"../../rtl",
"../../platform",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/vme64x-core",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core",
]
}
hdl/top/svec/svec_fine_delay_top.ucf 0 → 100644
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hdl/top/svec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ eca0894f
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "svec-fine-delay ",
syn_commit_id => "a3f676c402a931c43ed2654bddd7dbaf",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
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