The FMC DEL 1ns 2cha delay module provides two TTL pulse-outputs with
independently adjustable delay and pulse width. Pulses are triggered by
a common TTL input with adjustable threshold.
The timing is synchronized either to an external reference clock or an
internal 125 MHz VCXO (white rabbit compatible). Delay and pulse width
can be fine-adjusted with a resolution of 10 ps.
Signal paths have been optimized for low jitter and high frequency pulse
Two independently programmable output channels sharing a clock and trigger input.
SMA for all signals
Low Pin Count (LPC)
Input signal level
Clock: 150mVpp to 2Vpp. Trigger: 5V maximum, adjustable input threshold.
Output signal level
Clock: 800mVpp square wave. Output: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
| Date| * Event *|
| 04-01-2016 | Work on schematics started. |
| 27-01-2016 | First version of schematics ready for review. |
| 05-02-2016 | Layout started by CERN design office. |
| 08-02-2016 | Inclusion of project on OHWR. |
| 15-03-2016 | Layout completed. |
| 27-05-2016 | First two prototype boards received. |
| 10-08-2016 | First prototype boards under test. |
| 12-08-2016 | Some small
found but the board is functional. |
| 03-11-2016 | First two prototype boards deployed (on a SVEC) in LHC
for control of Schottky Monitor fast gates. |
| 19-01-2017 | Module presented at the BI Technical Board
| 01-05-2017 | Decision to change from surface mount SMA connectors to
through hole due to reliability issues. Amphenol 901-10138 selected
as a replacement. |
| 22-05-2017 | Version 3 design changes finished. |