fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave…

fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave default values (always zeros)

fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave…
fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave default values (always zeros)
e40c348a · Jan Pospisil · d9708bfe · e40c348a
Commit e40c348a authored Aug 23, 2016 by Jan Pospisil
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Showing with 5 additions and 5 deletions

Ad9512Control.vhd hdl/ffpg/rtl/Ad9512Control.vhd +5 -5

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--- a/hdl/ffpg/rtl/Ad9512Control.vhd
+++ b/hdl/ffpg/rtl/Ad9512Control.vhd
@@ -69,7 +69,7 @@ architecture syn of Ad9512Control is
    ------------------------------------------------------------------------
    signal ClockSelection: std_logic := '0';
-    signal ClockRatioMinus1_b: unsigned(ClockRatioMinus1_ib'range) := to_unsigned(2-1, ClockRatioMinus1_ib'length);
+    signal ClockRatioMinus1_b: unsigned(ClockRatioMinus1_ib'range) := to_unsigned(1-1, ClockRatioMinus1_ib'length);
    ------------------------------------------------------------------------
    -- AD9512 config registers
@@ -90,7 +90,7 @@ architecture syn of Ad9512Control is
    type t_Ad9512RegisterFiled is array (integer range <>) of t_Ad9512Register;
-    signal c_Ad9512Registers: t_Ad9512RegisterFiled(0 to c_Ad9512RegisterCount-1);
+    signal Ad9512Registers: t_Ad9512RegisterFiled(0 to c_Ad9512RegisterCount-1);
    -- calculate cycles according to provided ratio
    function f_CreateDivideReg1(ClockRatioMinus1_b: unsigned) return std_logic_vector is
@@ -199,7 +199,7 @@ begin
        end if;
    end process;
-    c_Ad9512Registers <= (
+    Ad9512Registers <= (
        -- power down unused output (OUT2)
        (X"3f", X"03"),
        -- select CLK1 input, power down CLK2 input
@@ -283,7 +283,7 @@ begin
        end if;
    end process;
-    pFsmOutputs: process (SeqCurrentState, SeqCnt) is begin
+    pFsmOutputs: process (SeqCurrentState, SeqCnt, Ad9512Registers) is begin
        WbAdr_b5 <= (others => '0');
        WbDatIn_b32 <= (others => '0');
        WbStb <= '0';
@@ -316,7 +316,7 @@ begin
            when S_WR_DATA =>
                WbAdr_b5 <= std_logic_vector(to_unsigned(16#00#, 5));
                WbDatIn_b32 <=
-                    f_Ad9512Register2WriteInstruction(c_Ad9512Registers(to_integer(SeqCnt)));
+                    f_Ad9512Register2WriteInstruction(Ad9512Registers(to_integer(SeqCnt)));
                WbStb <= '1';
                WbWe <= '1';
            when S_WR_CTRL =>