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FMC DEL 1ns 2cha
Commit bb9540eb authored by Jan Pospisil's avatar Jan Pospisil
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changed position of SPI slave initialization to prevent SS_N line glitch

parent 544ee006
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sw/FFPG_driver.py
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...@@ -129,9 +129,9 @@ def WaitForNotBusy(register, bit, timeOut, tries, message = '', polarity = 1): ...@@ -129,9 +129,9 @@ def WaitForNotBusy(register, bit, timeOut, tries, message = '', polarity = 1):
################################################################### ###################################################################
def SpiInit(): def SpiInit():
WbWrite('spi_ss', 1)
WbWrite('spi_divider', 2) # up to 150 MHz of FPGA system clock WbWrite('spi_divider', 2) # up to 150 MHz of FPGA system clock
WbWrite('spi_ctrl', 0x2618) WbWrite('spi_ctrl', 0x2618)
WbWrite('spi_ss', 1)
def SpiRead(register): def SpiRead(register):
WaitForNotBusy('spi_ctrl', 8, 0.001, 2, 'SPI read') WaitForNotBusy('spi_ctrl', 8, 0.001, 2, 'SPI read')
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