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F
FMC DEL 1ns 2cha
Commit b0c7b8f7 authored by Jan Pospisil's avatar Jan Pospisil
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added output timing constraints

parent 4a7a82b0
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Showing with 681 additions and 674 deletions
hdl/svec/syn/SvecFfpg.ucf
View file @ b0c7b8f7
......@@ -656,13 +656,20 @@ NET "Fmc1SpiAd9512Cs_on" IOSTANDARD = "LVCMOS25";
# System clock
NET "Clk20_ik" TNM_NET = Clk20_ik;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "Clk20_ik" 50 ns HIGH 50%;
NET "Clk20_ik" TNM_NET = tmn_Clk20_ik;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "tmn_Clk20_ik" 50 ns HIGH 50%;
# RF clock
NET "Fmc0ClkIn0P_ik" TNM_NET = Fmc0ClkIn0P_ik;
TIMESPEC TS_Fmc0ClkIn0P_ik = PERIOD "Fmc0ClkIn0P_ik" 4.97 ns HIGH 50%;
NET "Fmc0ClkIn0P_ik" TNM_NET = tmn_Fmc0ClkIn0P_ik;
TIMESPEC TS_Fmc0ClkIn0P_ik = PERIOD "tmn_Fmc0ClkIn0P_ik" 4.97 ns HIGH 50%;
OFFSET = OUT 2.22 ns AFTER "Fmc0ClkIn0P_ik";
TIMESPEC TS_Fmc0MultiCycle = FROM tmn_Fmc0ClkIn0P_ik TO PADS TS_Fmc0ClkIn0P_ik*3;
NET "Fmc1ClkIn0P_ik" TNM_NET = tmn_Fmc1ClkIn0P_ik;
TIMESPEC TS_Fmc1ClkIn0P_ik = PERIOD "tmn_Fmc1ClkIn0P_ik" 4.97 ns HIGH 50%;
OFFSET = OUT 2.22 ns AFTER "Fmc1ClkIn0P_ik";
TIMESPEC TS_Fmc1MultiCycle = FROM tmn_Fmc1ClkIn0P_ik TO PADS TS_Fmc1ClkIn0P_ik*3;
#===============================================================================
# False Path
......
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