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FMC DEL 1ns 2cha
Commits
a7f7c929
Commit
a7f7c929
authored
Aug 23, 2016
by
Jan Pospisil
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Plain Diff
fixed mode change detection
parent
5d4e76d9
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5 changed files
with
46 additions
and
37 deletions
+46
-37
DelayedPulseGeneratorsCdc.vhd
...g/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
+34
-4
FfpgCore.vhd
hdl/ffpg/rtl/FfpgCore.vhd
+0
-1
FfpgSlave.vhd
hdl/ffpg/rtl/FfpgSlave.vhd
+0
-2
WbSlaveWrapper.vhd
hdl/ffpg/rtl/WbSlaveWrapper.vhd
+10
-26
ffpg_csr.wb
hdl/ffpg/wb_gen/ffpg_csr.wb
+2
-4
No files found.
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
View file @
a7f7c929
...
...
@@ -29,10 +29,8 @@ entity DelayedPulseGeneratorsCdc is
TriggerLatency_ib16
:
in
unsigned
(
15
downto
0
);
TriggerLatencyLoad_i
:
in
std_logic
;
Ch1Mode_i
:
in
t_Mode
;
Ch1ModeLoad_i
:
in
std_logic
;
Ch1Running_o
:
out
std_logic
;
Ch2Mode_i
:
in
t_Mode
;
Ch2ModeLoad_i
:
in
std_logic
;
Ch2Running_o
:
out
std_logic
;
-- generation (FMC), synchronous to ClkRf_ik
ClkRf_ik
:
in
std_logic
;
...
...
@@ -51,7 +49,9 @@ architecture syn of DelayedPulseGeneratorsCdc is
signal
Overflow_b_slv
,
OverflowRf_b_slv
:
std_logic_vector
(
Overflow_ib16
'range
)
:
=
(
others
=>
'0'
);
signal
TriggerLatency_b_slv
,
TriggerLatencyRf_b_slv
:
std_logic_vector
(
TriggerLatency_ib16
'range
)
:
=
(
others
=>
'0'
);
signal
Ch1Mode_slv
,
Ch1ModeRf_slv
:
std_logic_vector
(
1
downto
0
);
signal
Ch1ModeLoad
:
std_logic
;
signal
Ch2Mode_slv
,
Ch2ModeRf_slv
:
std_logic_vector
(
1
downto
0
);
signal
Ch2ModeLoad
:
std_logic
;
-- ClkRf clock domain
signal
ResetRf_r
:
std_logic
;
...
...
@@ -97,7 +97,10 @@ begin
Edge_o
=>
TriggerRfPulse
);
-- Overflow
Overflow_b_slv
<=
std_logic_vector
(
Overflow_ib16
);
cOverflowSyncer
:
entity
work
.
RegSyncer
(
syn
)
port
map
(
ClkIn_ik
=>
Clk_ik
,
...
...
@@ -107,9 +110,13 @@ begin
Data_ob
=>
OverflowRf_b_slv
,
Load_o
=>
open
);
OverflowRf_b
<=
unsigned
(
OverflowRf_b_slv
);
-- TriggerLatency
TriggerLatency_b_slv
<=
std_logic_vector
(
TriggerLatency_ib16
);
cTriggerLatencySyncer
:
entity
work
.
RegSyncer
(
syn
)
port
map
(
ClkIn_ik
=>
Clk_ik
,
...
...
@@ -119,30 +126,53 @@ begin
Data_ob
=>
TriggerLatencyRf_b_slv
,
Load_o
=>
open
);
TriggerLatencyRf_b
<=
unsigned
(
TriggerLatencyRf_b_slv
);
-- Ch1Mode
Ch1Mode_slv
<=
f_ModeToSlv
(
Ch1Mode_i
);
cCh1ModeChange
:
entity
work
.
ChangeDetector
(
syn
)
port
map
(
Clk_ik
=>
Clk_ik
,
Signal_ib
=>
Ch1Mode_slv
,
Change_o
=>
Ch1ModeLoad
);
cCh1ModeSyncer
:
entity
work
.
RegSyncer
(
syn
)
port
map
(
ClkIn_ik
=>
Clk_ik
,
ClkOut_ik
=>
ClkRf_ik
,
Data_ib
=>
Ch1Mode_slv
,
Load_i
=>
Ch1ModeLoad
_i
,
Load_i
=>
Ch1ModeLoad
,
Data_ob
=>
Ch1ModeRf_slv
,
Load_o
=>
Ch1ModeLoadRf
);
Ch1ModeRf
<=
f_SlvToMode
(
Ch1ModeRf_slv
);
-- Ch2Mode
Ch2Mode_slv
<=
f_ModeToSlv
(
Ch2Mode_i
);
cCh2ModeChange
:
entity
work
.
ChangeDetector
(
syn
)
port
map
(
Clk_ik
=>
Clk_ik
,
Signal_ib
=>
Ch2Mode_slv
,
Change_o
=>
Ch2ModeLoad
);
cCh2ModeSyncer
:
entity
work
.
RegSyncer
(
syn
)
port
map
(
ClkIn_ik
=>
Clk_ik
,
ClkOut_ik
=>
ClkRf_ik
,
Data_ib
=>
Ch2Mode_slv
,
Load_i
=>
Ch2ModeLoad
_i
,
Load_i
=>
Ch2ModeLoad
,
Data_ob
=>
Ch2ModeRf_slv
,
Load_o
=>
Ch2ModeLoadRf
);
Ch2ModeRf
<=
f_SlvToMode
(
Ch2ModeRf_slv
);
----------------------------------
...
...
hdl/ffpg/rtl/FfpgCore.vhd
View file @
a7f7c929
-- TODO:
-- ! mode_load - not to assert when other control bit is changed
-- - frequency sense
library
ieee
;
...
...
hdl/ffpg/rtl/FfpgSlave.vhd
View file @
a7f7c929
...
...
@@ -188,10 +188,8 @@ begin
TriggerLatency_ib16
=>
WbRegsOutput
.
trigger_latency_o
,
TriggerLatencyLoad_i
=>
WbRegsOutput
.
trigger_latency_load_o
,
Ch1Mode_i
=>
f_SlvToMode
(
WbRegsOutput
.
control_ch1_mode_o
),
Ch1ModeLoad_i
=>
WbRegsOutput
.
control_ch1_mode_load_o
,
Ch1Running_o
=>
WbRegsInput
.
status_channel_1_running_i
,
Ch2Mode_i
=>
f_SlvToMode
(
WbRegsOutput
.
control_ch2_mode_o
),
Ch2ModeLoad_i
=>
WbRegsOutput
.
control_ch2_mode_load_o
,
Ch2Running_o
=>
WbRegsInput
.
status_channel_2_running_i
,
ClkRf_ik
=>
ClkRf_k
,
Ch1SetStream_o
=>
Ch1Set_o
,
...
...
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @
a7f7c929
...
...
@@ -38,8 +38,6 @@ architecture syn of WbSlaveWrapper is
signal
WbRegsOutput
:
t_ffpg_out_registers
;
-- registers for LOAD_EXT fields
signal
control_ch1_mode
:
std_logic_vector
(
1
downto
0
)
:
=
(
others
=>
'0'
);
signal
control_ch2_mode
:
std_logic_vector
(
1
downto
0
)
:
=
(
others
=>
'0'
);
signal
vcxo_voltage
:
unsigned
(
15
downto
0
)
:
=
(
others
=>
'0'
);
signal
clock_ratio_m1
:
unsigned
(
4
downto
0
)
:
=
(
others
=>
'0'
);
signal
ch1_delay_set
:
unsigned
(
9
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -50,8 +48,6 @@ architecture syn of WbSlaveWrapper is
signal
overflow
:
unsigned
(
15
downto
0
)
:
=
(
others
=>
'0'
);
signal
trigger_latency
:
unsigned
(
15
downto
0
)
:
=
(
others
=>
'0'
);
-- delayed load signals for LOAD_EXT fields
signal
control_ch1_mode_load
:
std_logic
:
=
'0'
;
signal
control_ch2_mode_load
:
std_logic
:
=
'0'
;
signal
vcxo_voltage_load
:
std_logic
:
=
'0'
;
signal
clock_ratio_m1_load
:
std_logic
:
=
'0'
;
signal
ch1_delay_set_load
:
std_logic
:
=
'0'
;
...
...
@@ -103,8 +99,6 @@ begin
pLocalRegs
:
process
(
Clk_ik
)
is
begin
if
rising_edge
(
Clk_ik
)
then
if
Reset_ir
=
'1'
then
control_ch1_mode_load
<=
'0'
;
control_ch2_mode_load
<=
'0'
;
vcxo_voltage_load
<=
'0'
;
clock_ratio_m1_load
<=
'0'
;
ch1_delay_set_load
<=
'0'
;
...
...
@@ -115,8 +109,6 @@ begin
overflow_load
<=
'0'
;
trigger_latency_load
<=
'0'
;
control_ch1_mode
<=
(
others
=>
'0'
);
control_ch2_mode
<=
(
others
=>
'0'
);
vcxo_voltage
<=
(
others
=>
'0'
);
clock_ratio_m1
<=
(
others
=>
'0'
);
ch1_delay_set
<=
(
others
=>
'0'
);
...
...
@@ -127,8 +119,6 @@ begin
overflow
<=
(
others
=>
'0'
);
trigger_latency
<=
(
others
=>
'0'
);
else
control_ch1_mode_load
<=
'0'
;
control_ch2_mode_load
<=
'0'
;
vcxo_voltage_load
<=
'0'
;
clock_ratio_m1_load
<=
'0'
;
ch1_delay_set_load
<=
'0'
;
...
...
@@ -139,14 +129,6 @@ begin
overflow_load
<=
'0'
;
trigger_latency_load
<=
'0'
;
if
WbRegsOutput
.
control_ch1_mode_load_o
=
'1'
then
control_ch1_mode
<=
WbRegsOutput
.
control_ch1_mode_o
;
control_ch1_mode_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
control_ch2_mode_load_o
=
'1'
then
control_ch2_mode
<=
WbRegsOutput
.
control_ch2_mode_o
;
control_ch2_mode_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
vcxo_voltage_load_o
=
'1'
then
vcxo_voltage
<=
WbRegsOutput
.
vcxo_voltage_o
;
vcxo_voltage_load
<=
'1'
;
...
...
@@ -187,13 +169,14 @@ begin
end
if
;
end
process
;
pInputRegisters
:
process
(
WbRegs_i
,
control_ch1_mode
,
control_ch2_mode
,
vcxo_voltage
,
clock_ratio_m1
,
ch1_delay_set
,
ch1_delay_reset
,
ch2_delay_set
,
ch2_delay_reset
,
trigger_threshold
,
overflow
,
trigger_latency
)
is
begin
pInputRegisters
:
process
(
WbRegs_i
,
vcxo_voltage
,
clock_ratio_m1
,
ch1_delay_set
,
ch1_delay_reset
,
ch2_delay_set
,
ch2_delay_reset
,
trigger_threshold
,
overflow
,
trigger_latency
)
is
begin
-- #!@& ISE doesn't know VHDL 2008 (... process (all) ...)
-- by default, all values are passed
WbRegsInput
<=
WbRegs_i
;
-- LOAD_EXT inputs are overwritten by local registers
WbRegsInput
.
control_ch1_mode_i
<=
control_ch1_mode
;
WbRegsInput
.
control_ch2_mode_i
<=
control_ch2_mode
;
WbRegsInput
.
vcxo_voltage_i
<=
vcxo_voltage
;
WbRegsInput
.
clock_ratio_m1_i
<=
clock_ratio_m1
;
WbRegsInput
.
ch1_delay_set_i
<=
ch1_delay_set
;
...
...
@@ -205,13 +188,15 @@ begin
WbRegsInput
.
trigger_latency_i
<=
trigger_latency
;
end
process
;
pOutputRegisters
:
process
(
WbRegsOutput
,
control_ch1_mode
,
control_ch2_mode
,
vcxo_voltage
,
clock_ratio_m1
,
ch1_delay_set
,
ch1_delay_reset
,
ch2_delay_set
,
ch2_delay_reset
,
trigger_threshold
,
overflow
,
trigger_latency
,
control_ch1_mode_load
,
control_ch2_mode_load
,
vcxo_voltage_load
,
clock_ratio_m1_load
,
ch1_delay_set_load
,
ch1_delay_reset_load
,
ch2_delay_set_load
,
ch2_delay_reset_load
,
trigger_threshold_load
,
overflow_load
,
trigger_latency_load
)
is
begin
pOutputRegisters
:
process
(
WbRegsOutput
,
vcxo_voltage
,
clock_ratio_m1
,
ch1_delay_set
,
ch1_delay_reset
,
ch2_delay_set
,
ch2_delay_reset
,
trigger_threshold
,
overflow
,
trigger_latency
,
vcxo_voltage_load
,
clock_ratio_m1_load
,
ch1_delay_set_load
,
ch1_delay_reset_load
,
ch2_delay_set_load
,
ch2_delay_reset_load
,
trigger_threshold_load
,
overflow_load
,
trigger_latency_load
)
is
begin
-- #!@& ISE doesn't know VHDL 2008 (... process(all) ...)
-- by default, all values are passed
WbRegs_o
<=
WbRegsOutput
;
-- LOAD_EXT inputs are overwritten by local registers
WbRegs_o
.
control_ch1_mode_o
<=
control_ch1_mode
;
WbRegs_o
.
control_ch2_mode_o
<=
control_ch2_mode
;
WbRegs_o
.
vcxo_voltage_o
<=
vcxo_voltage
;
WbRegs_o
.
clock_ratio_m1_o
<=
clock_ratio_m1
;
WbRegs_o
.
ch1_delay_set_o
<=
ch1_delay_set
;
...
...
@@ -221,8 +206,7 @@ begin
WbRegs_o
.
trigger_threshold_o
<=
trigger_threshold
;
WbRegs_o
.
overflow_o
<=
overflow
;
WbRegs_o
.
trigger_latency_o
<=
trigger_latency
;
WbRegs_o
.
control_ch1_mode_load_o
<=
control_ch1_mode_load
;
WbRegs_o
.
control_ch2_mode_load_o
<=
control_ch2_mode_load
;
WbRegs_o
.
vcxo_voltage_load_o
<=
vcxo_voltage_load
;
WbRegs_o
.
clock_ratio_m1_load_o
<=
clock_ratio_m1_load
;
WbRegs_o
.
ch1_delay_set_load_o
<=
ch1_delay_set_load
;
...
...
hdl/ffpg/wb_gen/ffpg_csr.wb
View file @
a7f7c929
...
...
@@ -118,9 +118,8 @@ peripheral {
prefix = "ch1_mode";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_
WRITE
;
access_dev = READ_
ONLY
;
};
field {
...
...
@@ -129,9 +128,8 @@ peripheral {
prefix = "ch2_mode";
type = SLV;
size = 2;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_
WRITE
;
access_dev = READ_
ONLY
;
};
field {
...
...
Write
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