improved timing by IOB registers packing for serial stream outputs

7f6d4fd3 · Jan Pospisil · 17c67fed · 7f6d4fd3 · 7f6d4fd3 · 7f6d4fd3
Commit 7f6d4fd3 authored Aug 11, 2016 by Jan Pospisil
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Showing with 35 additions and 34 deletions

ClkRfDomain.vhd hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd +20 -14

FfpgSlave.vhd hdl/ffpg/rtl/FfpgSlave.vhd +8 -13

SvecFfpg.xise hdl/svec/syn/SvecFfpg.xise +7 -7

No files found.
--- a/hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
+++ b/hdl/ffpg/rtl/DelayedPulseGenerator/ClkRfDomain.vhd
@@ -33,7 +33,7 @@ architecture syn of ClkRfDomain is
    constant c_MemLatency: integer := 2;
    signal LastStreamPosition: unsigned(Overflow_ib16'range);
-    signal TriggerLatencyPlusOne: unsigned(TriggerLatency_ib16'range);
+    signal TriggerLatencyPlusTwo: unsigned(TriggerLatency_ib16'range);
    signal GenerationEnable: std_logic;
    signal OutputEnable: std_logic;
@@ -51,14 +51,16 @@ architecture syn of ClkRfDomain is
    signal BitCounterOverflow, LoadShiftRegister: std_logic;
    signal SetStream, ResetStream: std_logic;
 begin
    -- for better timing
    pInputReg: process(Clk_ik) is begin
        if rising_edge(Clk_ik) then
            LastStreamPosition <= Overflow_ib16 - 1;
-            TriggerLatencyPlusOne <= TriggerLatency_ib16 + 1;
+            TriggerLatencyPlusTwo <= TriggerLatency_ib16 + 2;
+                -- +1 because of ???
+                -- +1 because of output registers on Set/ResetStream_o
        end if;
    end process;
@@ -86,7 +88,7 @@ begin
        end if;
    end process;
-    AddressEnableCounterSetValue <= TriggerLatencyPlusOne + c_MemLatency;
+    AddressEnableCounterSetValue <= TriggerLatencyPlusTwo + c_MemLatency;
    cAddressEnableCounter: entity work.Counter(syn)
        generic map (
            g_Width => 5
@@ -104,7 +106,7 @@ begin
    AddressCounterReset <=
        '1' when StreamPosition = (LastStreamPosition - c_MemLatency) else
        Reset_ir;
-    AddressCounterSetValue <= (TriggerLatencyPlusOne + c_MemLatency);
+    AddressCounterSetValue <= (TriggerLatencyPlusTwo + c_MemLatency);
    cAddressCounter: entity work.Counter(syn)
        generic map (
            g_Width => SetMemAddress_ob11'length
@@ -147,7 +149,7 @@ begin
            Reset_ir => StreamResetOrReset,
            Enable_i => GenerationEnable,
            Set_i => Trigger_i,
-            SetValue_ib => TriggerLatencyPlusOne,
+            SetValue_ib => TriggerLatencyPlusTwo,
            Overflow_o => open,
            Value_ob => StreamPosition
        );
@@ -161,7 +163,7 @@ begin
            Reset_ir => StreamResetOrReset,
            Enable_i => GenerationEnable,
            Set_i => Trigger_i,
-            SetValue_ib => TriggerLatencyPlusOne(4 downto 0),
+            SetValue_ib => TriggerLatencyPlusTwo(4 downto 0),
            Overflow_o => BitCounterOverflow,
            Value_ob => open
        );
@@ -198,12 +200,16 @@ begin
            LoadEnable_i => LoadShiftRegister
        );
-    SetStream_o <=
+    pOutputRegs: process (Clk_ik) is begin
-        SetStream when OutputEnable = '1' else
+        if rising_edge(Clk_ik) then
-        '0';
+            if OutputEnable = '1' then
+                SetStream_o <= SetStream;
-    ResetStream_o <=
+                ResetStream_o <= ResetStream;
-        ResetStream when OutputEnable = '1' else
+            else
-        '0';
+                SetStream_o <= '0';
+                ResetStream_o <= '0';
+            end if;
+        end if;
+    end process;
 end architecture;
\ No newline at end of file
--- a/hdl/ffpg/rtl/FfpgSlave.vhd
+++ b/hdl/ffpg/rtl/FfpgSlave.vhd
@@ -67,7 +67,6 @@ architecture syn of FfpgSlave is
    signal WbRegsInput: t_ffpg_in_registers;
    signal WbRegsOutput: t_ffpg_out_registers;
-    signal Ch1Set, Ch1Res, Ch2Set, Ch2Res: std_logic;
    signal LedSignal_b: std_logic_vector(4 downto 1);
 begin
@@ -176,11 +175,9 @@ begin
            ModeLoad_i => WbRegsOutput.control_ch1_mode_load_o,
            Running_o => WbRegsInput.status_channel_1_running_i,
            ClkRf_ik => ClkRf_k,
-            SetStream_o => Ch1Set,
+            SetStream_o => Ch1Set_o,
-            ResetStream_o => Ch1Res
+            ResetStream_o => Ch1Res_o
        );
-    Ch1Set_o <= Ch1Set;
-    Ch1Res_o <= Ch1Res;
    cDelayedPulseGeneratorCh2: entity work.DelayedPulseGenerator(syn)
        port map (
@@ -201,11 +198,9 @@ begin
            ModeLoad_i => WbRegsOutput.control_ch2_mode_load_o,
            Running_o => WbRegsInput.status_channel_2_running_i,
            ClkRf_ik => ClkRf_k,
-            SetStream_o => Ch2Set,
+            SetStream_o => Ch2Set_o,
-            ResetStream_o => Ch2Res
+            ResetStream_o => Ch2Res_o
        );
-    Ch2Set_o <= Ch2Set;
-    Ch2Res_o <= Ch2Res;
    ----------------------------------
    -- Clock selection (temporary)
@@ -230,11 +225,11 @@ begin
            Data_ob(0) => TriggerRf
        );
-    -- OUT1
+    -- OUT1 - enabled and running
-    LedSignal_b(1) <= Ch1Set;
+    LedSignal_b(1) <= WbRegsInput.status_channel_1_running_i and WbRegsOutput.control_ch1_oe_o;
-    -- OUT2
+    -- OUT2 - enabled and running
-    LedSignal_b(2) <= Ch2Set;
+    LedSignal_b(2) <= WbRegsInput.status_channel_2_running_i and WbRegsOutput.control_ch2_oe_o;
    -- TRIG IN
    LedSignal_b(3) <= TriggerRf;

--- a/hdl/svec/syn/SvecFfpg.xise
+++ b/hdl/svec/syn/SvecFfpg.xise
@@ -47,7 +47,7 @@
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -87,7 +87,7 @@
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -121,7 +121,7 @@
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -130,7 +130,7 @@
    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -191,7 +191,7 @@
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
@@ -217,7 +217,7 @@
    <property xil_pn:name="Output File Name" xil_pn:value="SvecTopFfpg" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -356,7 +356,7 @@
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->