Split PCI/VME drivers

46befee2 · Tom Levens · 01d4ddcf · 46befee2 · 46befee2
Commit 46befee2 authored Feb 28, 2023 by Tom Levens
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fmc_fpg_pci_hw_desc.csv sw/driver/fmc_fpg_pci_hw_desc.csv +58 -0

fmc_fpg_vme_hw_desc.csv sw/driver/fmc_fpg_vme_hw_desc.csv +1 -1

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--- a/sw/driver/fmc_fpg_pci_hw_desc.csv
+++ b/sw/driver/fmc_fpg_pci_hw_desc.csv
+#Encore Driver GEnerator version 3.1
+
+# Module description table
+hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
+    FMC-FPG,     fmc_fpg,   1.0.0-pci,       3.1, PCI,     LE, FMC Fast Pulse Generator
+
+# Device Identification table definition
+vendor, device, args
+0x10DC, 0x01A3, subvendor=0x1A39 subdevice=0x0004
+
+# BARs definition table
+res_def_name, type, res_no, args, description
+   registers,  MEM,      0,     ,
+
+# Block definition table
+block_def_name, type,             name,  offset, rwmode, dwidth, depth, mask, flags, description
+           csr,  REG,           status,     0x0,      r,     32,   0x1,     ,      , Status register
+           csr,  REG,          control,     0x4,     rw,     32,   0x1,     ,      , Control register
+           csr,  REG,     vcxo_voltage,     0x8,     rw,     32,   0x1,     ,      , VCXO voltage
+           csr,  REG,   clock_ratio_m1,     0xc,     rw,     32,   0x1,     ,      , Clock ratio minus 1
+           csr,  REG,    ch1_delay_set,    0x10,     rw,     32,   0x1,     ,      , CH1 set delay
+           csr,  REG,    ch1_delay_res,    0x14,     rw,     32,   0x1,     ,      , CH1 reset delay
+           csr,  REG,    ch2_delay_set,    0x18,     rw,     32,   0x1,     ,      , CH2 set delay
+           csr,  REG,    ch2_delay_res,    0x1c,     rw,     32,   0x1,     ,      , CH2 reset delay
+           csr,  REG,   trig_threshold,    0x20,     rw,     32,   0x1,     ,      , Trigger threshold voltage
+           csr,  REG,         overflow,    0x24,     rw,     32,   0x1,     ,      , Overflow
+           csr,  REG, ch1_trig_latency,    0x28,     rw,     32,   0x1,     ,      , CH1 trigger latency
+           csr,  REG,        frequency,    0x2c,      r,     32,   0x1,     ,      , Clock frequency
+           csr,  REG,            debug,    0x30,      r,     32,   0x1,     ,      , Debug register
+           csr,  REG,          version,    0x34,      r,     32,   0x1,     ,      , FFPG version
+           csr,  REG, ch2_trig_latency,    0x38,     rw,     32,   0x1,     ,      , CH2 trigger latency
+           csr,  REG,       fine_delay,    0x3c,     rw,     32,   0x1,     ,      , AD9512 OUT4 fine delay
+           csr,  REG,      ch1_set_mem,  0x2000,     rw,     32, 0x800,     ,      , CH1 SET serial stream
+           csr,  REG,      ch1_res_mem,  0x4000,     rw,     32, 0x800,     ,      , CH1 RES serial stream
+           csr,  REG,      ch2_set_mem,  0x6000,     rw,     32, 0x800,     ,      , CH2 SET serial stream
+           csr,  REG,      ch2_res_mem,  0x8000,     rw,     32, 0x800,     ,      , CH2 RES serial stream
+
+# Block definition table
+block_def_name, type,             name,  offset, rwmode, dwidth, depth, mask, flags, description
+    spi_master,  REG,           status,     0x0,     rw,     32,   0x1,     ,      , Status register
+    spi_master,  REG,          config1,     0x4,     rw,     32,   0x1,     ,      , Config 1 register
+    spi_master,  REG,          config2,     0x8,     rw,     32,   0x1,     ,      , Config 2 register
+    spi_master,  REG,        shift_out,     0xc,     rw,     32,   0x1,     ,      , Shift out register
+    spi_master,  REG,         shift_in,    0x10,     rw,     32,   0x1,     ,      , Shift in register
+
+# Block definition table
+block_def_name, type,             name,  offset, rwmode, dwidth, depth, mask, flags, description
+onewire_master,  REG,         ctrl_sta,     0x0,     rw,     32,   0x1,     ,      , Control/status register
+onewire_master,  REG,              cdr,     0x4,     rw,     32,   0x1,     ,      , Clock dividers register
+
+# Block instances table
+block_inst_name, block_def_name, res_def_name,  offset, description
+ onewire_master, onewire_master,    registers, 0x21000, OneWire master
+     spi_master,     spi_master,    registers, 0x22000, WB SPI master
+            csr,            csr,    registers, 0x30000, Control/status registers
+
+# Reg roles table
+reg_role, reg_name, block_def_name, args
--- a/sw/driver/fmc_fpg_hw_desc.csv
+++ b/sw/driver/fmc_fpg_hw_desc.csv
@@ -2,7 +2,7 @@

 # Module description table
 hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
-    FMC-FPG,     fmc_fpg,       1.0.0,       3.1, VME,     BE, FMC Fast Pulse Generator
+    FMC-FPG,     fmc_fpg,   1.0.0-vme,       3.1, VME,     BE, FMC Fast Pulse Generator

 # BARs definition table
 res_def_name, type, res_no,                                              args, description