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FMC DEL 1ns 2cha
Commit 446b00fb authored by Jan Pospisil's avatar Jan Pospisil
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added whole SPI read test

parent 67788178
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Showing with 43 additions and 17 deletions
hdl/ffpg/sim/testbench/Testbench.sv
View file @ 446b00fb
...@@ -43,6 +43,7 @@ module Testbench; ...@@ -43,6 +43,7 @@ module Testbench;
parameter c_ClkPeriod = 1e9/`CLK_FREQ; // in [ns] parameter c_ClkPeriod = 1e9/`CLK_FREQ; // in [ns]
bit Clk_k, Reset_r; bit Clk_k, Reset_r;
bit SpiLoopback;
FfpgInterface LocalInterface(Clk_k, Reset_r); FfpgInterface LocalInterface(Clk_k, Reset_r);
...@@ -83,8 +84,8 @@ module Testbench; ...@@ -83,8 +84,8 @@ module Testbench;
.Ch2Res_o(LocalInterface.Fmc.Ch2Res), .Ch2Res_o(LocalInterface.Fmc.Ch2Res),
.Trigger_i(LocalInterface.Fmc.Trigger), .Trigger_i(LocalInterface.Fmc.Trigger),
.SpiAd9512Sclk_o(), // not tested so far .SpiAd9512Sclk_o(), // not tested so far
.SpiAd9512Mosi_o(), // not tested so far .SpiAd9512Mosi_o(SpiLoopback), // not tested so far
.SpiAd9512Miso_i(), // not tested so far .SpiAd9512Miso_i(SpiLoopback), // not tested so far
.SpiAd9512Cs_on(), // not tested so far .SpiAd9512Cs_on(), // not tested so far
.Clk2Sel_o(), // not tested so far .Clk2Sel_o(), // not tested so far
.Onewire_io(), // not tested so far .Onewire_io(), // not tested so far
......
hdl/ffpg/sim/testbench/TestbenchPackage.sv
View file @ 446b00fb
...@@ -748,6 +748,8 @@ package TestbenchPackage; ...@@ -748,6 +748,8 @@ package TestbenchPackage;
class SeqAd9512 extends ReportingSequence #(td_wb_tx); class SeqAd9512 extends ReportingSequence #(td_wb_tx);
`uvm_object_utils(SeqAd9512) `uvm_object_utils(SeqAd9512)
logic [31:0] spiBaseAddress = 32'h00002000;
function new (string name = ""); function new (string name = "");
super.new(name); super.new(name);
endfunction endfunction
...@@ -761,22 +763,45 @@ package TestbenchPackage; ...@@ -761,22 +763,45 @@ package TestbenchPackage;
tx.data = data; tx.data = data;
finish_item(tx); finish_item(tx);
endtask endtask
task readWbRegister(logic [31:0] address, output logic [31:0] data);
td_wb_tx tx = td_wb_tx::type_id::create("tx");
start_item(tx);
assert(tx.randomize());
tx.direction_e = WB_B3_DIR_READ;
tx.address = address;
finish_item(tx);
data = tx.data;
endtask
task waitForFreeSpi;
int free = 0;
int tries = 0;
logic [31:0] status;
while (!free) begin
readWbRegister(spiBaseAddress, status);
status = (status>>16) & 'h7;
free = (status == 4 || status == 0) ? 1 : 0;
tries++;
assert(tries < 500);
#500;
end
// `uvm_info("SeqAd9512", $sformatf("Wait for free SPI - %d tries.", tries), UVM_LOW)
endtask
task body; task body;
logic [31:0] spiBaseAddress = 32'h00002000; logic [31:0] data;
writeWbRegister(spiBaseAddress + 1, 32'hC0000018); // read reg 0x34
writeWbRegister(spiBaseAddress + 2, 32'h50005); waitForFreeSpi;
writeWbRegister(spiBaseAddress + 3, 32'h204a5500); writeWbRegister(spiBaseAddress + 1*4, 32'hC0000018);
#10000; writeWbRegister(spiBaseAddress + 2*4, 32'h00050005);
writeWbRegister(spiBaseAddress + 3*4, 32'hA0340000);
// // read CONFIG1 waitForFreeSpi;
// tx = td_wb_tx::type_id::create("tx"); readWbRegister(spiBaseAddress + 4*4, data);
// start_item(tx); `uvm_info("SeqAd9512", $sformatf("Data read from SPI master core: 0x%08x", data), UVM_LOW)
// assert(tx.randomize());
// tx.direction_e = WB_B3_DIR_READ; #100;
// tx.address = 32'h00002001;
// finish_item(tx);
endtask endtask
......
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