fixed pulseGenerator for cases when g_PulseMinWidth==1

3db419eb · Jan Pospisil · d4ca5732 · 3db419eb
Commit 3db419eb authored Apr 04, 2017 by Jan Pospisil
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Showing with 35 additions and 29 deletions

pulseGenerator.vhd hdl/ffpg/rtl/pulseGenerator.vhd +35 -29

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--- a/hdl/ffpg/rtl/pulseGenerator.vhd
+++ b/hdl/ffpg/rtl/pulseGenerator.vhd
@@ -8,7 +8,7 @@ use ieee.std_logic_1164.all;

 entity PulseGenerator is
    generic (
-		g_PulseMinWidth: integer := 3 -- multiply of 'Clk_ik' periods
+        g_PulseMinWidth: positive := 3 -- multiple of 'Clk_ik' periods
    );
    port (
        Clk_ik: in std_logic;
@@ -24,6 +24,7 @@ architecture base of PulseGenerator is

 begin

+    gMore: if g_PulseMinWidth > 1 generate
        pShiftRegister: process (Clk_ik) begin
            if rising_edge(Clk_ik) then
                if Reset_ir = '1' then
@@ -43,5 +44,10 @@ begin
            end loop;
            Pulse_o <= Pulse;
        end process;
+    end generate;
+    
+    gOne: if g_PulseMinWidth = 1 generate
+        Pulse_o <= Signal_i;
+    end generate;

 end architecture;