field { name = "Pulse generator channel 1 running";
description = "Pulse generator channel 1 running\n0: channel 1 is not running\n1: channel 1 is running, pulses are generated";
prefix = "channel_1_running";
type = BIT;
...
...
@@ -72,8 +63,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Pulse generator channel 2 running";
field { name = "Pulse generator channel 2 running";
description = "Pulse generator channel 2 running\n0: channel 2 is not running\n1: channel 2 is running, pulses are generated";
prefix = "channel_2_running";
type = BIT;
...
...
@@ -81,8 +71,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Input clock stable";
field { name = "Input clock stable";
description = "Indicates the stability of the input clock.\n0: input clock not present or not stable\n1: input clock present and stable";
prefix = "input_clock_stable";
type = BIT;
...
...
@@ -91,12 +80,10 @@ peripheral {
}
};
reg {
name = "Control register";
reg { name = "Control register";
prefix = "control";
field {
name = "Clock source selection";
field { name = "Clock source selection";
description = "0 (default): external clock used (connector on the front panel)\n1: FPGA loop clock used\n2: on-board VCXO clock used";
prefix = "clock_selection";
type = SLV;
...
...
@@ -105,24 +92,21 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "CH1 output enable";
field { name = "CH1 output enable";
prefix = "ch1_oe";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "CH2 output enable";
field { name = "CH2 output enable";
prefix = "ch2_oe";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "CH1 mode selection";
field { name = "CH1 mode selection";
description = "0 (default): stopped (no output generated)\n1: continuous (non-stop memory looping)\n2: one-shot (loop memory just once)";
prefix = "ch1_mode";
type = SLV;
...
...
@@ -131,8 +115,7 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "CH2 mode selection";
field { name = "CH2 mode selection";
description = "0 (default): stopped (no output generated)\n1: continuous (non-stop memory looping)\n2: one-shot (loop memory just once)";
prefix = "ch2_mode";
type = SLV;
...
...
@@ -141,8 +124,7 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "LED test";
field { name = "LED test";
description = "If set to 1, all LEDs on the FFPG front panel will be blinking.";
prefix = "led_test";
type = BIT;
...
...
@@ -150,15 +132,13 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "AD9512 Synchronization";
field { name = "AD9512 Synchronization";
description = "When written with 1 AD9512 dividers synchronization is performed. It automatically clear to 0.";
prefix = "ad9512_sync";
type = MONOSTABLE;
};
field {
name = "AD9512 OUT4 fine delay enable";
field { name = "AD9512 OUT4 fine delay enable";
description = "If set to 1, fine delay on OUT4 output of AD9512 is enabled. Fine delay itself can be set in a separate register.";
prefix = "fine_delay_enable";
type = BIT;
...
...
@@ -168,13 +148,11 @@ peripheral {
};
reg {
name = "VCXO voltage register";
reg { name = "VCXO voltage register";
prefix = "vcxo_voltage";
description = "This register value D determines output voltage of the VCXO DAC.\nVoltage should be V_OUT = D * 5 / 65536 [V] (see datasheet), but is limited by 3.3 V supply voltage of the DAC.";
field {
name = "VCXO voltage register value";
field { name = "VCXO voltage register value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
...
...
@@ -183,13 +161,11 @@ peripheral {
};
};
reg {
name = "Clock ratio-1 register";
reg { name = "Clock ratio-1 register";
prefix = "clock_ratio_m1";
description = "Clock ratio specifies the frequency of the serial stream clock generated by the AD9512 clock divider: f_generated = f_input / (RATIO+1). This ratio is used for all clocks generated on the FMC card. Permitted values are 0-31 which renders to actual ratio 1-32.";
field {
name = "Clock ratio-1";
field { name = "Clock ratio-1";
type = UNSIGNED;
size = 5;
load = LOAD_EXT;
...
...
@@ -198,13 +174,11 @@ peripheral {
};
};
reg {
name = "SET delay configuration (channel 1)";
reg { name = "SET delay configuration (channel 1)";
prefix = "ch1_delay_set";
description = "10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH1 pulse delay";
field {
name = "CH1 SET delay";
field { name = "CH1 SET delay";
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
...
...
@@ -214,13 +188,11 @@ peripheral {
};
reg {
name = "RES delay configuration (channel 1)";
reg { name = "RES delay configuration (channel 1)";
prefix = "ch1_delay_reset";
description = "10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH1 pulse width";
field {
name = "CH1 RES delay";
field { name = "CH1 RES delay";
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
...
...
@@ -229,13 +201,11 @@ peripheral {
};
};
reg {
name = "SET delay configuration (channel 2)";
reg { name = "SET delay configuration (channel 2)";
prefix = "ch2_delay_set";
description = "10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH2 pulse delay";
field {
name = "CH2 SET delay";
field { name = "CH2 SET delay";
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
...
...
@@ -245,13 +215,11 @@ peripheral {
};
reg {
name = "RES delay configuration (channel 2)";
reg { name = "RES delay configuration (channel 2)";
prefix = "ch2_delay_reset";
description = "10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH2 pulse width";
field {
name = "CH2 RES delay";
field { name = "CH2 RES delay";
type = UNSIGNED;
size = 10;
load = LOAD_EXT;
...
...
@@ -260,13 +228,11 @@ peripheral {
};
};
reg {
name = "Trigger threshold voltage register";
reg { name = "Trigger threshold voltage register";
prefix = "trigger_threshold";
description = "This register value D determines output voltage of the trigger threshold DAC.\nVoltage should be V_OUT = D * 5 / 65536 [V] (see datasheet).";
field {
name = "Trigger threshold voltage register value";
field { name = "Trigger threshold voltage register value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
...
...
@@ -275,13 +241,11 @@ peripheral {
};
};
reg {
name = "Overflow";
reg { name = "Overflow";
prefix = "overflow";
description = "Overflow index for serial stream memory. When this index is reach when looping the memory, memory index is reset back to 0.";
field {
name = "Overflow value";
field { name = "Overflow value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
...
...
@@ -290,13 +254,11 @@ peripheral {
};
};
reg {
name = "Trigger latency (channel 1)";
reg { name = "Trigger latency (channel 1)";
prefix = "ch1_trigger_latency";
description = "The latency of the trigger in number of clock cycles of the serial stream clock, for channel 1. When trigger is received, serial stream memory pointer is set to this value.";
field {
name = "Trigger latency value";
field { name = "Trigger latency value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
...
...
@@ -305,13 +267,11 @@ peripheral {
};
};
reg {
name = "Clock frequency";
reg { name = "Clock frequency";
prefix = "frequency";
description = "Frequency of the input clock in Hz.";
field {
name = "Clock frequency value";
field { name = "Clock frequency value";
type = UNSIGNED;
size = 32;
access_bus = READ_ONLY;
...
...
@@ -319,13 +279,11 @@ peripheral {
};
};
reg {
name = "Debug register";
reg { name = "Debug register";
prefix = "debug";
description = "For internal use only, do not use!";
field {
name = "Debug field";
field { name = "Debug field";
type = UNSIGNED;
size = 32;
access_bus = READ_ONLY;
...
...
@@ -333,13 +291,11 @@ peripheral {
};
};
reg {
name = "Gateware version";
reg { name = "Gateware version";
prefix = "version";
description = "Version of the current gateware in form of major.minor.revision";
field {
name = "Revision";
field { name = "Revision";
prefix = "revision";
type = UNSIGNED;
size = 12;
...
...
@@ -347,8 +303,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Minor version";
field { name = "Minor version";
prefix = "minor";
type = UNSIGNED;
size = 10;
...
...
@@ -356,8 +311,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Major version";
field { name = "Major version";
prefix = "major";
type = UNSIGNED;
size = 10;
...
...
@@ -366,13 +320,11 @@ peripheral {
};
};
reg {
name = "Trigger latency (channel 2)";
reg { name = "Trigger latency (channel 2)";
prefix = "ch2_trigger_latency";
description = "The latency of the trigger in number of clock cycles of the serial stream clock, for channel 2. When trigger is received, serial stream memory pointer is set to this value.";
field {
name = "Trigger latency value";
field { name = "Trigger latency value";
type = UNSIGNED;
size = 16;
load = LOAD_EXT;
...
...
@@ -381,13 +333,11 @@ peripheral {
};
};
reg {
name = "AD9512 OUT4 fine delay";
reg { name = "AD9512 OUT4 fine delay";
prefix = "fine_delay";
description = "Value of the AD9512 OUT4 output fine delay. The actual delay applied to the OUT4 output has an offset, i.e. it is non-zero even when zero is written to this register (when the fine delay is enabled - see the status register for the enable bit).";
