Move all channel related registers to a separate Cheby/EDGE block to
simplify the driver interfacing. Unfortunately it's not possible to put
the memories there otherwise the memory space ends up being too big.

This project uses lower_case rather than CamelCase, so adapt the naming
of the new registers for consistency.

Fix formatting/etc to minimise diffs when testing the auto-generation of
the driver from Cheby.

Need to allow control logic to run when RF PLL is in reset or not
locked. Hence needed to restructure the resets.

RF logic reset is now under main reset + software control.
So is RF I/O interface reset. Added also ready status signal, so SW can
determine when I/O interface is ready.

System/WB side of things reset by main reset, as before.

Closes #9

Closes #10

Not yet tested!

It doesn't seem to be used?