Missing connections for memory

hdl/ffpg/rtl/FfpgCore.vhd

@@ -293,7 +293,6 @@ begin
     ----------------------------------
     -- shared memory address and read enable
     WbRegsInput.csr_ch2_mem_adr_i <= WbRegsInput.csr_ch1_mem_adr_i;
-    WbRegsInput.csr_ch2_mem_data_rd_i <= WbRegsInput.csr_ch1_mem_data_rd_i;
 
     WbRegsInput.csr_ch1_mem_clk_i <= ClkRf_k;
     WbRegsInput.csr_ch2_mem_clk_i <= ClkRf_k;
@@ -304,8 +303,9 @@ begin
             Reset_ir => Reset_r,
             Trigger_i => TriggerCombined,
             MemAddress_ob => WbRegsInput.csr_ch1_mem_adr_i,
-            MemReadStrobe_o => WbRegsInput.csr_ch1_mem_data_rd_i,
+            Ch1MemReadStrobe_o => WbRegsInput.csr_ch1_mem_data_rd_i,
             Ch1MemData_ib => WbRegsOutput.csr_ch1_mem_data_dat_o(9 downto 0),
+            Ch2MemReadStrobe_o => WbRegsInput.csr_ch2_mem_data_rd_i,
             Ch2MemData_ib => WbRegsOutput.csr_ch2_mem_data_dat_o(9 downto 0),
 
             Resync_i => WbRegsOutput.csr_sw_trigger_resync,