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FMC ADC 100M 14b 4cha
Commit f8b05f5d authored by Federico Vaga's avatar Federico Vaga
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doc: conversion from texinfo and remove obsolete stuff 

It is a big patch touching many things. You may want to compare it
with the previous texinfo file.
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent f2640a29
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doc/Makefile
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......@@ -17,4 +17,8 @@ help:
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
$(MAKE) -C gateware/regs all
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
clean:
$(MAKE) -C gateware/regs clean
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
doc/gateware/index.rst
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doc/gateware/memory-map.rst 0 → 100644
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..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
==============
The Memory Map
==============
Following the memory map for the part of the ADC design that drives
the FMC ADC 100M modules.
.. raw:: html
:file: regs/fmc_adc_mezzanine_mmap.htm
Supported Designs
=================
Here you can find the complete memory MAP for the supported
designs. This will include the ADC register as well as the carrier
registers and any other component used in an FMC ADC 100M design.
.. toctree::
:maxdepth: 1
:caption: Table of Contents
spec_ref_fmc_adc_100M
svec_ref_fmc_adc_100M
doc/manual/regs/Makefile → doc/gateware/regs/Makefile
View file @ f8b05f5d
SOURCES = $(wildcard *.cheby)
SOURCES = $(wildcard *.cheby) ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
TARGETS = $(SOURCES:.cheby=.htm)
all: $(TARGETS)
......@@ -6,10 +6,8 @@ all: $(TARGETS)
.PHONY: $(TARGETS) clean
$(TARGETS): %.htm : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-doc=$@ --doc html
# @cheby -i $< --gen-doc=$(@:.htm=.rst) --doc rest
# @cheby -i $< --gen-doc=$(@:.htm=.md) --doc md
@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-doc=$(shell basename $@) --doc html
clean:
@rm -f *.md *.rst *.htm
doc/gateware/spec_ref_fmc_adc_100M.rst 0 → 100644
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..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
=================
SPEC FMC ADC 100M
=================
.. raw:: html
:file: regs/spec_ref_fmc_adc_100Ms_doc.htm
doc/gateware/svec_ref_fmc_adc_100M.rst 0 → 100644
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..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
=================
SVEC FMC ADC 100M
=================
.. raw:: html
:file: regs/svec_ref_fmc_adc_100Ms_doc.htm
doc/index.rst
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......@@ -13,3 +13,4 @@ FMC-ADC-100M-14B-4CHA documentation
introduction
software/index
gateware/index
gateware/memory-map
doc/manual/Makefile deleted 100644 → 0
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#
# Makefile for the documentation directory
#
# Copyright 1994,2000,2010,2011 Alessandro Rubini <rubini@linux.it>
#
#################
# There is not basenames here, all *.in are considered input
INPUT = $(wildcard *.in)
TEXI = $(INPUT:.in=.texi)
INFO = $(INPUT:.in=.info)
HTML = $(INPUT:.in=.html)
TXT = $(INPUT:.in=.txt)
PDF = $(INPUT:.in=.pdf)
ALL = $(INFO) $(HTML) $(TXT) $(PDF)
MAKEINFO ?= makeinfo
%.texi: %.in
@rm -f $@
sed -f ./infofilter $< > $@
emacs -batch --no-site-file -l fixinfo $@
chmod -w $@
%.pdf: %.texi
texi2pdf --batch $<
%.info: %.texi
$(MAKEINFO) $< -o $@
%.html: %.texi
$(MAKEINFO) --html --no-split -o $@ $<
%.txt: %.texi
$(MAKEINFO) --no-headers $< > $@
##############################################
.PHONY: all images check terse clean install
.INTERMEDIATE: $(TEXI)
all: images $(ALL)
$(MAKE) terse
images::
if [ -d images ]; then $(MAKE) -C images || exit 1; fi
check: _err.ps
gs -sDEVICE=linux -r320x200x16 $<
terse:
for n in cp fn ky pg toc tp vr aux log; do rm -f *.$$n; done
rm -f *~
clean: terse
rm -f $(ALL) $(TEXI)
# add the other unused targets, so the rule in ../Makefile works
modules install modules_install:
doc/manual/fixinfo deleted 100644 → 0
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;; use:
;; emacs -batch -l ./fixinfo.el <file>
;; or, better:
;; emacs -batch --no-site-file -l ./fixinfo.el <file>
(defun fixinfo (file)
(find-file-other-window file)
(message (concat "Maxing texinfo tree in " file))
(texinfo-all-menus-update)
(texinfo-every-node-update)
(save-buffer)
(kill-buffer (current-buffer))
)
;; loop over command line arguments
(mapcar 'fixinfo command-line-args-left)
(kill-emacs)
doc/manual/fmc_adc_100Ms_csr.tex deleted 100644 → 0
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doc/manual/fmc_adc_eic.tex deleted 100644 → 0
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: disable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: disable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: enable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: enable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/O @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is enabled@*read 0: interrupt 'Trigger interrupt' is disabled
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is enabled@*read 0: interrupt 'End of acquisition interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/W @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
doc/manual/fmcadc100m14b4cha_gateware_manual.in deleted 100644 → 0
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doc/manual/infofilter deleted 100644 → 0
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#! /usr/bin/sed -f
# allow "%" as a comment char, but only at the beginning of the line
s/^%/@c /
#s/[^\\]%.*$//
s/^\\%/%/
#preserve blanks and braces in @example blocks
/^@example/,/^@end example/ s/{/@{/g
/^@example/,/^@end example/ s/}/@}/g
/^@example/,/^@end example/ p
/^@example/,/^@end example/ d
/^@smallexample/,/^@end smallexample/ s/{/@{/g
/^@smallexample/,/^@end smallexample/ s/}/@}/g
/^@smallexample/,/^@end smallexample/ p
/^@smallexample/,/^@end smallexample/ d
# remove leading blanks
s/^[ ]*//
doc/manual/sdb_ids.txt deleted 100644 → 0
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@verbatim
integration: vid=0xCE42, did=0x47c786a2
wb crossbar: vid=0x0651, did=0xe6a542c9
wb bridge : vid=0x0651, did=0xeef0b198
vic : vid=0xCE42, did=0x00000013
onewire : vid=0xCE42, did=0x779c5443
spec_csr : vid=0xCE42, did=0x00000603
svec_csr : vid=0xCE42, did=0x00006603
timetag : vid=0xCE42, did=0x00000604
fmc_eic : vid=0xCE42, did=0x26ec6086
i2c : vid=0xCE42, did=0x123c5443
spi : vid=0xCE42, did=0xe503947e
adc_csr : vid=0xCE42, did=0x00000608
dma_eic : vid=0xCE42, did=0xd5735ab4
dma_ctrl : vid=0xCE42, did=0x00000601
ddr_addr : vid=0xCE42, did=0x10006611
ddr_data : vid=0xCE42, did=0x10006610
@end verbatim
doc/manual/spec/carrier_csr.tex deleted 100644 → 0
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab
PCB revision
@item @code{15...4}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC_PRES}
@tab @code{X} @tab
FMC presence
@item @code{1}
@tab R/O @tab
@code{P2L_PLL_LCK}
@tab @code{X} @tab
GN4142 core P2L PLL status
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR3_CAL_DONE}
@tab @code{X} @tab
DDR3 calibration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc_pres} @tab 0: FMC slot is populated@*1: FMC slot is not populated.
@item @code{p2l_pll_lck} @tab 0: not locked@*1: locked.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr3_cal_done} @tab 0: not done@*1: done.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{LED_GREEN}
@tab @code{0} @tab
Green LED
@item @code{1}
@tab R/W @tab
@code{LED_RED}
@tab @code{0} @tab
Red LED
@item @code{2}
@tab R/W @tab
@code{DAC_CLR_N}
@tab @code{0} @tab
DAC clear
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0}
@tab @code{0} @tab
State of the reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
doc/manual/spec/dma_eic.tex deleted 100644 → 0
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: disable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: disable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: enable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: enable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/O @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is enabled@*read 0: interrupt 'DMA done interrupt' is disabled
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is enabled@*read 0: interrupt 'DMA error interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/W @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
doc/manual/spec_wb_tree.txt deleted 100644 → 0
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@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- dma controller
0x1100 |-- onewire master
0x1200 |-- spec csr
0x1300 |-- vic
0x1400 |-- dma eic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c master
0x3100 | |-- spi master
0x3200 | |-- i2c master
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc-adc eic
0x3600 | |-- timetag core
@end verbatim
doc/manual/svec/carrier_csr.tex deleted 100644 → 0
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab
PCB revision
@item @code{15...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC0_PRES}
@tab @code{X} @tab
FMC 1 presence
@item @code{1}
@tab R/O @tab
@code{FMC1_PRES}
@tab @code{X} @tab
FMC 2 presence
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR0_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 4 calibration status
@item @code{4}
@tab R/O @tab
@code{DDR1_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 5 calibration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_pres} @tab 0: FMC slot 1 is populated@*1: FMC slot 1 is not populated.
@item @code{fmc1_pres} @tab 0: FMC slot 2 is populated@*1: FMC slot 2 is not populated.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0}
@tab @code{0} @tab
State of the FMC 1 reset line
@item @code{1}
@tab R/W @tab
@code{FMC1}
@tab @code{0} @tab
State of the FMC 2 reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@item @code{fmc1} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
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@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- i2c
0x1100 |-- onewire
0x1200 |-- svec csr
0x1300 |-- vic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c
0x3100 | |-- spi
0x3200 | |-- i2c
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc_eic
0x3600 | |-- timetag
0x4000 |-- ddr_addr (fmc slot 1)
0x5000 |-- ddr_data (fmc slot 1)
0x6000 |-- bridge (fmc slot 2) -> crossbar (sdb records)
0x7000 | |-- i2c
0x7100 | |-- spi
0x7200 | |-- i2c
0x7300 | |-- adc csr
0x7400 | |-- onewire
0x7500 | |-- fmc_eic
0x7600 | |-- timetag
0x8000 |-- ddr_addr (fmc slot 2)
0x9000 |-- ddr_data (fmc slot 2)
@end verbatim
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{CTL} @tab
VIC Control Register
@item @code{0x4} @tab
REG @tab
@code{RISR} @tab
Raw Interrupt Status Register
@item @code{0x8} @tab
REG @tab
@code{IER} @tab
Interrupt Enable Register
@item @code{0xc} @tab
REG @tab
@code{IDR} @tab
Interrupt Disable Register
@item @code{0x10} @tab
REG @tab
@code{IMR} @tab
Interrupt Mask Register
@item @code{0x14} @tab
REG @tab
@code{VAR} @tab
Vector Address Register
@item @code{0x18} @tab
REG @tab
@code{SWIR} @tab
Software Interrupt Register
@item @code{0x1c} @tab
REG @tab
@code{EOIR} @tab
End Of Interrupt Acknowledge Register
@item @code{0x20 - 0x3f}
@tab MEM @tab @code{IVT_RAM} @tab Interrupt Vector Table
@end multitable
@regsection @code{CTL} - VIC Control Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{ENABLE}
@tab @code{0} @tab
VIC Enable
@item @code{1}
@tab R/W @tab
@code{POL}
@tab @code{0} @tab
VIC output polarity
@item @code{2}
@tab R/W @tab
@code{EMU_EDGE}
@tab @code{0} @tab
Emulate Edge sensitive output
@item @code{18...3}
@tab R/W @tab
@code{EMU_LEN}
@tab @code{0} @tab
Emulated Edge pulse timer
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ENABLE} @tab @bullet{} 1: enables VIC operation@*@bullet{} 0: disables VIC operation
@item @code{POL} @tab @bullet{} 1: IRQ output is active high@*@bullet{} 0: IRQ output is active low
@item @code{EMU_EDGE} @tab @bullet{} 1: Forces a low pulse of @code{EMU_LEN} clock cycles at each write to @code{EOIR}. Useful for edge-only IRQ controllers such as Gennum.@*@bullet{} 0: Normal IRQ master line behavior
@item @code{EMU_LEN} @tab Length of the delay (in @code{clk_sys_i} cycles) between write to @code{EOIR} and re-assertion of @code{irq_master_o}.
@end multitable
@regsection @code{RISR} - Raw Interrupt Status Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{RISR}
@tab @code{X} @tab
Raw interrupt status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RISR} @tab Each bit reflects the current state of corresponding IRQ input line.@*@bullet{} read 1: interrupt line is currently active@*@bullet{} read 0: interrupt line is inactive
@end multitable
@regsection @code{IER} - Interrupt Enable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IER}
@tab @code{0} @tab
Enable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IER} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IDR} - Interrupt Disable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IDR}
@tab @code{0} @tab
Disable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IDR} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IMR} - Interrupt Mask Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IMR}
@tab @code{X} @tab
IRQ disabled/enabled
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IMR} @tab @bullet{} read 1: interrupt associated with read bit is enabled@*@bullet{} read 0: interrupt is disabled
@end multitable
@regsection @code{VAR} - Vector Address Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{VAR}
@tab @code{X} @tab
Vector Address
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{VAR} @tab Address of pending interrupt vector, read from Interrupt Vector Table
@end multitable
@regsection @code{SWIR} - Software Interrupt Register
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SWIR}
@tab @code{0} @tab
SWI interrupt mask
@end multitable
@regsection @code{EOIR} - End Of Interrupt Acknowledge Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{EOIR}
@tab @code{0} @tab
End of Interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{EOIR} @tab Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
@end multitable
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