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FMC ADC 100M 14b 4cha
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doc: conversion from texinfo and remove obsolete stuff 

It is a big patch touching many things. You may want to compare it
with the previous texinfo file.
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
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doc/Makefile
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......@@ -17,4 +17,8 @@ help:
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
$(MAKE) -C gateware/regs all
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
clean:
$(MAKE) -C gateware/regs clean
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
doc/gateware/index.rst
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The Gateware
============
.. toctree::
:maxdepth: 1
:caption: Contents
About Source Code
=================
Build from Sources
------------------
The fmc-adc hdl design make use of the ``hdlmake`` tool. It
automatically fetches the required hdl cores and libraries. It also
generates Makefiles for synthesis/par and simulation.
Here is the procedure to build the FPGA binary image from the hdl
source.::
# Install ``hdlmake`` (version 2.1).
# Get fmc-adc hdl sources.
git clone git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha-gw.git <src_dir>
# Goto the synthesis directory.
cd <src_dir>/hdl/<carrier>/syn/
# Fetch the dependencies and generate a synthesis Makefile.
hdlmake
# Perform synthesis, place, route and generate FPGA bitstream.
make
Source Code Organisation
------------------------
hdl/rtl/
ADC specific hdl sources.
hdl/adc/wb_gen/
ADC specific ``wbgen2`` sources, html documentation and C header
file.
hdl/ip_cores/
Location of fetched and generated hdl cores and libraries.
hdl/<carrier>/rtl/
Carrier related hdl sources.
hdl/<carrier>/wb_gen/
Carrier related ``wbgen2`` sources, html documentation and C header
file.
hdl/<carrier>/syn/
Synthesis directory for selected carrier. This is where the
synthesis top manifest and the ISE project are stored. For each
release, the synthesis, place&route and timing reports are also
saved here.
hdl/<carrier>/sim/, hdl/<carrier>/testbench/
Carrier related simulation files and testbenches.
hdl/<carrier>/chipscope/
Carrier related Chipscope projects used for debug purpose.
It could happen that a hdl source directory contains extra source files
that are not used in the current gateware release. In order to identify
the source files used in a given release, refer to the Manifest.py
files.
Dependencies
------------
The fmc-adc gateware depends on the following hdl cores and libraries:
`General Cores`_, `DDR3 SP6 core`_, `GN4124 core`_ (SPEC only),
`SPEC`_ (SPEC only) `VME64x Slave`_ (SVEC only), `SVEC`_ (SVEC only).
These dependencies are managed with GIT submodules. Whenever you checkout
a different branch remember to update the submodules as well.::
git submodule sync
git submodule update
Architecture
============
This chapter describes the internal blocks of the FPGA for both SPEC
(PCIe) and SVEC (VME64x) carriers. The gateware is designed around one
or several `OpenCores Wishbone`_ bus interconnects.
SPEC (PCIe carrier)
-------------------
In the PCIe version of the gateware, all blocks (except the memory
controller) are connected to the PCIe bridge interface using the same
Wishbone bus (*main* bus). The ADC samples are written and read
to/from the DDR memory using separate Wishbone bus interconnects. Due
to its size, the DDR memory is not mapped on the *main* Wishbone bus
and can only be accessed through DMA. The following figure illustrates
the fmc-adc gateware architecture on the SPEC carrier. A crossbar from
the `General Cores`_ library is used to map the slaves in the Wishbone
address space.
.. figure:: ../fig/spec_fw_arch.svg
:alt: SPEC FMC-ADC gateware architecture
FMC-ADC gateware architecture on SPEC carrier.
There are three different Wishbone bus interconnects in the design.
Mapped WB bus (blue)
This bus connects all the peripherals to the GN4142 core.
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
ADC core to memory controller (orange)
This bus is used to write samples from the ADC core to the DDR memory.
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
Memory controller to GN4124 core (red)
This bus is used to read samples from the DDR memory.
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
The next table shows the Wishbone slaves mapping and hierarchy. The
first column represents the byte address offset from the start of the
Wishbone address space (BAR 0).
::
0x1000 |-- dma controller
0x1100 |-- onewire master
0x1200 |-- spec csr
0x1300 |-- vic
0x1400 |-- dma eic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c master
0x3100 | |-- spi master
0x3200 | |-- i2c master
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc-adc eic
0x3600 | |-- timetag core
Note that some of the cores from the `General Cores`_ library are
based on cores from `OpenCores`_. Therefore, the documentation for
those cores is hosted on the OpenCores website.
Clock Domains
~~~~~~~~~~~~~
The SPEC version of the fmc-adc design has five different clock domains.
They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+=================+=================+=================+=================+
| ``sys_clk_125`` | Main system | 125.00 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ``ddr_clk`` | DDR interface | 333.33 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ``fs_clk`` | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) |
+-----------------+-----------------+-----------------+-----------------+
| ``serdes_clk`` | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) |
| | clock | | |
+-----------------+-----------------+-----------------+-----------------+
| ``p2l_clk`` | Local bus clock | 200.00 MHz | 200MHz GN4124 |
| | | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
GN4124 Core
~~~~~~~~~~~
This block is the interface between the `GN4124`_
local bus and the other blocks in the FPGA. The GN4124 is a four lane
PCI Express Generation 1.1 bridge. In addition to the PHY, it also
contains the data link and transaction layers. The GN4124 bridge is used
to access the FPGA registers, but also to generate MSI interrupts and
re-program the FPGA. BAR4 (Base Address Register) allows access to the
GN4124 internal registers. BAR0 is connected to the local bus and
therefore allows access to the FPGA.
The GN4124 core is made of a local bus interface with the GN4124 chip, a
Wishbone bus master mapped to BAR0 and a DMA controller. The DMA
controller has two Wishbone ports, a Wishbone slave to configure the DMA
controller and a Wishbone master. In the fmc-adc gateware, the master
port is connected to the DDR memory controller. The GN4124 Wishbone
interfaces (masters and slave) are 32-bit data width and 32-bit word
aligned addresses.
.. note::
It would not be beneficial to insert an address converter (for
non-interleaved data read) between the GN4124 core and the memory
controller, because the DDR memory access is not efficient when
reading non-consecutive addresses.
SVEC (VME64x carrier)
---------------------
In the VME64x version of the gateware, all blocks are connected to the
VME64x core using a single Wishbone bus. Here the DDR memory is not
accessed through DMA, but using a indirect addressing scheme explained
later in `DDR Memory Controller <#DDR-Memory-Controller>`__. A crossbar
from the general-cores\ `:sup:`11` <#FOOT11>`__ library is used to map
the slaves in the Wishbone address space.
.. figure:: ../fig/svec_fw_arch.svg
:alt:
FMC-ADC gateware architecture on SVEC carrier.
There are three different Wishbone bus interconnects in the design.
Mapped WB bus (blue)
This bus connects all the peripheral to the VME64x core.
Data: 32-bit, address: 32-bit (word aligned),
Clock: system clock (125MHz) and system clock / 2 (62.5MHz), see note below.
ADC cores to memory controllers (2x, orange)**
These two buses are used to write samples from the ADC cores to the DDR
memories.
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
.. note::
The VME64x core cannot work with a clock frequency as high as
125MHz, therefore it is clocked with half the system clock
frequency. As the fmc-adc core needs 125MHz to work properly, a
Wishbone clock crossing component is inserted between the VME64x core
and the first Wishbone crossbar component. With this topology, only
the VME64x core runs at a lower frequency.
The next table shows the Wishbone slaves mapping and hierarchy. The
first column represents the byte address offset from the start of the
Wishbone address space.
::
0x1000 |-- i2c
0x1100 |-- onewire
0x1200 |-- svec csr
0x1300 |-- vic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c
0x3100 | |-- spi
0x3200 | |-- i2c
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc_eic
0x3600 | |-- timetag
0x4000 |-- ddr_addr (fmc slot 1)
0x5000 |-- ddr_data (fmc slot 1)
0x6000 |-- bridge (fmc slot 2) -> crossbar (sdb records)
0x7000 | |-- i2c
0x7100 | |-- spi
0x7200 | |-- i2c
0x7300 | |-- adc csr
0x7400 | |-- onewire
0x7500 | |-- fmc_eic
0x7600 | |-- timetag
0x8000 |-- ddr_addr (fmc slot 2)
0x9000 |-- ddr_data (fmc slot 2)
Clock Domains
~~~~~~~~~~~~~
The SPEC version of the fmc-adc design has five different clock domains.
They are listed in the following table.
+-----------------+-----------------+-----------------+-----------------+
| Name | Description | Frequency | Source |
+=================+=================+=================+=================+
| sys_clk_125 | Main system | 125.00 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| sys_clk_62_5 | System clock / | 62.50 MHz | 20MHz TCXO |
| | 2 | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| ddr_clk | DDR interface | 333.33 MHz | 20MHz TCXO |
| | clock | | (carrier) |
+-----------------+-----------------+-----------------+-----------------+
| fs_clk | Sampling clock | 100.00 MHz | 400MHz LTC2174 |
| | | | (mezzanine) |
+-----------------+-----------------+-----------------+-----------------+
| serdes_clk | ADC data | 800.00 MHz | 400MHz LTC2174 |
| | de-serialiser | | (mezzanine) |
| | clock | | |
+-----------------+-----------------+-----------------+-----------------+
VME64x Core
~~~~~~~~~~~
The VME64x core implements a VME slave on one side and a Wishbone
pipelined master on the other side. For more information about the
VME64x core, visit the OHWR page.
Common Cores
------------
DDR Memory Controller
~~~~~~~~~~~~~~~~~~~~~
The memory controller block is the interface between the 256MB DDR3
memory located on the carrier boards and the other blocks in the FPGA.
It is basically a MCB core (Memory Controller Block) generated with
`Xilinx CoreGen`_ and an additional wrapper implementing two Wishbone
slave interfaces.
One of the Wishbone slave interfaces is connected to the ADC core. In
the SPEC gateware, the other Wishbone slave interface is connected to
the DMA Wishbone master of the GN4124 core. In the SVEC gateware, the
other slave Wishbone interface is connected to an indirect addressing
block.
This block consists of an address pointer register and a data FIFO. To
access the DDR memory, the gateware sets the address pointer and then
reads/writes data using the FIFO. On each access to the FIFO, the
address pointer is automatically incremented.
+----------+-------------+------------+-------------+
| WB Slave | Description | Data width | Access type |
+==========+=============+============+=============+
| ``0`` | ADC core | 64-bit | Write only |
+----------+-------------+------------+-------------+
| ``1`` | host side | 32-bit | Read/write |
+----------+-------------+------------+-------------+
The memory controller side connected to the chip is 16-bit wide, clocked
at 333.33 MHz DDR. This gives a maximum bandwidth of 1333.33 MB/s. Each
of the four ADC channels requires 200 MB/s (16-bits per sample, 100
MHz), for a total of 800 MB/s.
In the current design, the two Wishbone ports have the same priority and
the arbitration is done with a simple round-robin. Therefore, samples
stored in the DDR memory should not be read during an acquisition.
Vectored Interrupt Controller (VIC)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. note::
FIXME explain how interrupts are connected to spec-base/svec-base.
There is something to be said about EDGE/LEVEL, or polarity.
FMC-ADC Core
------------
The ADC core is the main block of the design. On the mezzanine interface
side, it takes a data flow from the `LTC2174`_ ADC chip, an external
trigger and controls the analogue switches to select the input range or
calibration mode. On the internal interface side, it has a Wishbone
master to write data to the DDR memory controller. It also has a
Wishbone slave to access the internal components.
The internal detailed functioning of this block is described further in
the document (See `Configuration`_, `Calibration`_ and `Acquisition`_).
Sampling clock
~~~~~~~~~~~~~~
The sampling frequency is determined by a `Si570`_ programmable oscillator
located on the fmc-adc mezzanine. By default, the sampling clock is
100MHz (oscillator factor default value), but it can be changed to any
frequency from 10MHz to 105MHz. The lower bound is defined by the Si570
oscillator while the upper bound is limited by the LTC2174 ADC itself.
The Si570 clock output is connected to the LTC2174 ADC. Then the data
clock (DCO) output of the LTC2174 is connected to the FPGA. The data
clock is four times the sampling clock. The sampling clock (``fs_clk``)
and the ADC data de-serialiser clock (``serdes_clk``) are derived from
the data clock using a PLL (internal to the FPGA).
**Note:** The internal PLL expects a 400MHz input frequency (define in
the hdl code), therefore the sampling frequency has to be 100MHz and
can’t be changed dynamically.
The ADC core implements a sampling clock frequency meter. The measured
frequency (in Hz) can be read via a register (see `ADC Core
Registers <#ADC-Core-Registers>`__).
Time-tagging Core
~~~~~~~~~~~~~~~~~
This block allows time-tagging of important events in the ADC core. It
is based on two free-running counters; a seconds counter and a 125MHz
system clock ticks counter. The system clock ticks counter is also
called coarse counter. These two counters are accessible in read/write
via a Wishbone interface.
For example, the host computer can use the OS time to set the seconds
counter and simply reset the coarse counter. It is planned, in a later
release, to set the time-tagging core counters using the White Rabbit
core.
A time-tag is made of four 32-bit words; meta-data, seconds, coarse,
fine. The fine field is always set to zero and the meta-data register
does not contain useful information, only random data for debugging
purposes.
The following events are time-tagged:
- Trigger
- Acquisition start
- Acquisition stop
- Acquisition end
.. note::
The trigger time tag corresponds to the moment when the acquisition
state machine leaves the ``WAIT_TRIG`` state.
.. note::
The trigger time-tag is also stored in the data memory, after the
post-trigger samples. This allows to always have a trigger time-tag,
even in multi-shot mode (retrieving the time-tag using the trigger
interrupt was not fast enough in certain cases).
.. note::
If during an acquisition no stop command is issued (normal case),
the acquisition stop time-tag is not updated.
The register description can be found in annex `Time-tagging Core
Registers <#Time_002dtagging-Core-Registers>`__.
FMC-ADC Control and Status Registers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This block contains control and status registers related to the fmc-adc
core. The registers description can be found in annex (`ADC Core
Registers <#ADC-Core-Registers>`__).
Mezzanine SPI Master
~~~~~~~~~~~~~~~~~~~~
This SPI master controls the LTC2174 ADC and the four MAX5442 offset
DACs. The following table shows how the peripherals are wired to the
core. This block is based on an OpenCores design.
+------------------+---------------------------+
| SPI slave select | Peripheral |
+==================+===========================+
| ``0`` | LTC2174 ADC |
+------------------+---------------------------+
| ``1`` | MAX5442 DAC for channel 1 |
+------------------+---------------------------+
| ``2`` | MAX5442 DAC for channel 2 |
+------------------+---------------------------+
| ``3`` | MAX5442 DAC for channel 3 |
+------------------+---------------------------+
| ``4`` | MAX5442 DAC for channel 4 |
+------------------+---------------------------+
This block is clocked by the system clock (125 MHz). Therefore for a
SCLK of ~620 kHz, the divider configuration is ``DIVIDER=100``.
::
f_sclk = f_sys / ((DIVIDER+1) * 2)
Mezzanine 1-wire Master
~~~~~~~~~~~~~~~~~~~~~~~
This 1-wire master controls the DS18B20 thermometer chip located on the
mezzanine board. This chip also contains a unique 64-bit identifier.
This block is based on an OpenCores design\ `:sup:`21` <#FOOT21>`__.
This block is clocked by the system clock (125 MHz). Therefore the
dividers configuration are ``CDR_N=624`` and ``CDR_O=124``.
Mezzanine I2C Master
~~~~~~~~~~~~~~~~~~~~
This I2C master controls the Si570 programmable oscillator chip
located on the mezzanine board. This chip is used to produce the ADC
sampling clock. This block is based on an OpenCores design.
+-------------------+-------------------------------+
| I2C slave address | Peripheral |
+===================+===============================+
| ``0x55`` | Si570 programmable oscillator |
+-------------------+-------------------------------+
This block is clocked by the system clock (125 MHz). Therefore for a SCL
clock of 100 kHz, the prescaler configuration is ``PRESCALER=249``.
::
PRESCALER = f_sys / (5 * f_scl) - 1
FMC-ADC Embedded Interrupt Controller (EIC)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. note::
FIXME check if this is gone
The fmc-adc EIC gathers the interrupts from the ADC core. There are two
inputs to the fmc-adc EIC:
- ° **Trigger**: This interrupt signals that a valid trigger arrived
while the acquisition state machine was in the ``WAIT_TRIG`` state.
- ° **Acquisition end**: This interrupt signals the end of an
acquisition. In case of multi-shot acquisition, it occurs at the end
of the last shot.
The two inputs are multiplexed and the result is forwarded to the VIC
(`Vectored Interrupt Controller
(VIC) <#Vectored-Interrupt-Controller-_0028VIC_0029>`__). Interrupt
sources can be masked using the enable and disable registers. An
interrupt is cleared by writing a one to the corresponding bit of the
status register.
The registers description can be found in annex `FMC-ADC Embedded
Interrupt Controller
Registers <#FMC_002dADC-Embedded-Interrupt-Controller-Registers>`__).
Configuration
-------------
The following figure is a block diagram of the ADC core part in the
sampling clock domain. It contains an ADC data stream de-serialiser,
an offset and gain correction block (for ADC data), an under-sampling
block and a trigger unit. The four channels’ data and the trigger
signal are synchronised to the system clock domain using a FIFO. The
configuration signals coming from registers in the system clock domain
are synchronised to the sampling clock within the Wishbone slave
(``wbgen2`` feature).
.. figure:: ../fig/adc_core_fs_clk.svg
:alt: ADC core diagram (sampling clock domain)
ADC core diagram (sampling clock domain).
The LTC2174 is by default configured in *2-Lane Output Mode, 16-Bit
Serialization*. In the fmc-adc application, this default configuration
is kept. Following an extract from the LTC2174 datasheet illustrating
the *2-Lane Output Mode, 16-Bit Serialization* waveforms.
.. figure:: ../fig/ltc2174_mode.pdf
:alt: LTC2174 data output mode waveforms.
LTC2174 data output mode waveforms.
There are two 800Mbit/s lanes per ADC channel. Eight data lanes in
total and the frame rate (FR) lane are fed to a de-serialiser in the
FPGA. The frame rate signal is used to align the de-serialiser to data
words. The four channel data (16-bit) are concatenated together to
form a 64-bit vector. As shown in the figure above, the two LSB bits
of a data word are always set to zero.
.. warning::
Upon reset the ADC defaults to “offset binary” representation for
the channel data. However, the ADC core expects “two’s
complement”. Therefore, it is important to change the relevant
configuration register in the ADC itself. When using the provided
FMC-ADC driver, this is done automatically during driver initialisation.
Control and Status Registers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Writing one to to the ``FMC_CLK_OE`` field of the ADC core control
register enables the sampling clock (Si570 chip). Also, in order to use
the input offset DACs, the ``OFFSET_DAC_CLR_N`` field must be set to
one.
The field ``MAN_BITSLIP`` allows to ’manually’ control the ADC data
alignment in the de-serialiser. When ``TEST_DATA_EN`` is set, the ADC
core writes the address pointer to the memory instead of the ADC
samples. The fields ``TRIG_LED`` and ``ACQ_LED`` allows to control the
FMC front panel LEDs. Those four fields are for test purpose only and
must stay zero in normal operation.
When the sampling clock is enabled, the ``SERDES_PLL`` and
``SERDES_SYNCED`` field from the ADC core status register must be set to
one.
Input Ranges
~~~~~~~~~~~~
`Figure 4.3 <#fig_003aanalogue_005finput>`__ shows a simplified
schematic diagram of the analogue input stage used for each channel.
Each input can be independently configured with one of the three
available ranges; 100mV, 1V, 10V. Each range is defined as the maximum
peak-to-peak input voltage. Independently to the selected range, a
50ohms termination can be added to each input.
In addition to the three ranges for normal operation, there are three
more configurations used for offset calibration of each range.
Opto-isolated analogue switches are used to apply the various
configurations. They are represented by standard switch symbols in the
simplified schematic.
.. figure:: ../fig/analogue_input.pdf
:alt: Simplified schematic diagram of the analogue input stage
Simplified schematic diagram of the analogue input stage.
Only the following input switch configurations are valid. For all others
switch configurations, the behavior is not defined and therefore
shouldn’t be used.
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| SW[7.1] | SW7 | SW6 | SW5 | SW4 | SW3 | SW2 | SW1 | Description |
+=========+=====+=====+=====+=====+=====+=====+=====+================================+
| 0x23 | OFF | ON | OFF | X | OFF | ON | ON` | 100mV range |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x11 | OFF | OFF | ON` | X | OFF | OFF | ON` | 1V range |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x45 | ON | OFF | OFF | X | ON | OFF | ON` | 10V range |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x42 | ON | OFF | OFF | X | OFF | ON | OFF | 100mV range offset calibration |
+-------+-------+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x40 | ON | OFF | OFF | X | OFF | OFF | OFF | 1V range offset calibration |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x44 | ON | OFF | OFF | X | ON | OFF | OFF | 10V range offset calibration |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x00 | X | OFF | OFF | OFF | X | X | OFF | Input disconnected |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
| 0x08 | X | X | X | ON` | X | X | X`` | 50ohm termination |
+---------+-----+-----+-----+-----+-----+-----+-----+--------------------------------+
Input Offset
~~~~~~~~~~~~
Each channel has a 16-bit DAC allowing to apply a dc offset to the input
signal. The voltage range of the DAC is 10V (-5V to +5V) and is
independent from the selected input range. The following equation shows
how to convert a digital value written to a DAC to an offset voltage.
::
v_dac = (v_ref * d_dac/0x8000) - v_ref
Where:
v_ref = DAC's voltage reference = 5V
d_dac = Digital value written to the DAC
v_dac = DAC voltage
Example:
0xFFFF => 4.999V
0x8000 => 0.000V
0x0000 => -5.000V
The following equation shows the relation between the input voltage and
the offset (applied by the DAC). Note that the offset from the DAC is
subtracted from the input voltage.
::
v_out = v_in - v_dac
Where:
v_in = Input voltage
v_dac = DAC voltage
v_out = Output voltage (to filter and ADC)
Trigger
~~~~~~~
The trigger unit is made of two hardware and one software sources. The
hardware and software paths can be enabled independently. The two paths
are then or’ed together to drive a delay generator. The delay generator
allows to insert a predefined number of sampling clock periods before
the trigger is forwarded to the acquisition state machine. the next
figure shows a simplified digram of the trigger unit.
.. figure:: ../fig/trigger_unit.svg
:alt: Trigger unit diagram
Trigger unit diagram.
The hardware trigger source can be either internal (based on an ADC
input channel) or external (dedicated trigger input). For both internal
and external hardware triggers, the polarity can be selected between
positive and negative slope (resp. rising and falling edge). By default
the polarity is set to positive slope.
The external trigger input is synchronised to the sampling clock. The
external trigger pulse must be at least one sampling clock cycle wide.
To use the internal trigger source, both the ADC input channel and the
threshold should be configured. By default, channel 1 is selected and
the threshold is set to 0. Note that the threshold is 16-bit signed
(two’s complement). This figure sketches the internal hardware trigger
threshold behavior.
.. figure:: ../fig/trig_hw_int.svg
:alt: Internal hardware trigger threshold
Internal hardware trigger threshold.
Furthermore, a glitch filter can be applied to the threshold detection.
The glitch filter is useful to trigger on noisy signals. In order to
help setting the glitch filter, an internal trigger test mode can be
activated. When the test mode is enabled, data from channels 2, 3 and 4
is replaced as follow:
+-----------+--------------------------------------+
| Channel 2 | Input signal over threshold |
+-----------+--------------------------------------+
| Channel 3 | Input signal over threshold filtered |
+-----------+--------------------------------------+
| Channel 4 | Trigger |
+-----------+--------------------------------------+
The software trigger source consists of a pulse generated when a write
cycle is detected on the *Software trigger* register. For further
information on the trigger configuration registers see `ADC Core
Registers <#ADC-Core-Registers>`_.
Undersampling
~~~~~~~~~~~~~
The undersampling block is simply validating one in N samples and
forwarding it to the acquisition logic. The number (N) is configured in
the *Sample rate* register. If N > 1, then the trigger pulse is aligned
to the next valid sample. If N = 1 all the samples are valid and
therefore the trigger is always aligned. A value of N = 0 is treated as
N = 1 in the gateware.
Calibration
-----------
Calibration is done once during the production tests. It can be repeated
afterwards with the production test suite (PTS) and the corresponding
testbench. The calibration process gives the following four values per
channel and per input range:
- ADC gain correction
- ADC offset correction
- DAC gain correction
- DAC offset correction
Note that the temperature during the calibration process is also
measured. This could be used for later temperature compensated
calibration value computing.
Calibration data storage
~~~~~~~~~~~~~~~~~~~~~~~~
All the calibration values are stored in the FmcAdc100m14b4cha EEPROM
(`24AA64`_). In addition to the calibration values, the EEPROM also
contains mandatory IPMI records specified in the FMC Standard VITA
57.1.
+-------------+-----------+-----------+---------------------+
| Byte offset | File name | File Type | Description |
+=============+===========+===========+=====================+
| ``0x0`` | IPMI-FRU | binary | IPMI records |
+-------------+-----------+-----------+---------------------+
| ``0x100`` | calib | binary | Calibration values |
+-------------+-----------+-----------+---------------------+
Calibration Data Usage
~~~~~~~~~~~~~~~~~~~~~~
ADC Calibration
^^^^^^^^^^^^^^^
Two registers per channel are implemented in the FPGA for ADC gain and
offset correction. When an input range is selected, the corresponding
gain/offset correction values must be loaded from the EEPROM to those
registers.
.. figure:: ../fig/offset_gain_corr.svg
:alt: ADC offset and gain correction block
ADC offset and gain correction block.
The offset register takes a 16-bit signed value. The gain register takes
a 16-bit fixed point value. The fixed point format is as follow:
.. figure:: ../fig/adc_gain_format.svg
:alt: ADC gain register format
ADC gain register format.
After the offset and gain corrections are applied, the signal is
saturated to a user-programmable value. One register per channel allows
to set the saturation value. The saturation register takes a 15-bit
unsigned value. From this value, two ’symmetrical’ 16-bit signed numbers
are derived and taken as the saturation boundaries.
.. warning::
Because the default value (on FPGA start-up) is not
configurable in cheby, the gain, offset and saturation registers are
set to 0x0 at start-up. Therefore, the driver has to initialise those
registers.
.. note::
After gain and offset correction, the two LSB of the data words can
be different from zero.
.. note::
It is usually the driver’s task to read the calibration data
from the FMC EEPROM and load them to the corresponding registers. This
has to be done once at start-up and then every time the input range is
changed.
DAC Calibration
^^^^^^^^^^^^^^^
The DAC value is only set once before an acquisition. Therefore, there
is no need to implement the gain and offset correction in the FPGA. The
software controlling the fmc-adc must apply the DAC gain and offset
correction prior to writing a value to the DAC. As for the ADC
correction values, there is one pair (offset, gain) of DAC correction
values per input range.
Below is the formula to calculate the corrected DAC value (applying gain
and offset correction):
::
c_val = ((val + offset) * gain/0x8000) + 0x8000
where:
c_val = corrected value to write to DAC (16-bit unsigned)
val = value from user (16-bit signed)
offset = DAC offset calibration value from EEPROM (16-bit signed)
gain = DAC gain calibration value from EEPROM (16-bit fixed point)
Acquisition
-----------
This chapter describes the two modes of acquisition, single-shot and
multi-shot. It also explains how the software is expected to control the
fmc-adc acquisitions.
The heart of the acquisition logic is a state machine driven by user
commands (start, stop), the trigger signal and counters events
(e.g. pre-trig done, etc...). The ADC samples are routed along a
datapath (bold arrows), which depends on the acquisition mode. It is
explained in detail in the `Single-shot Mode`_ and `Multi-shot
Mode`_. The four channels data and the trigger are concatenated
together and fed to a FIFO to be synchronised between the sampling
clock domain and the system clock domain. Even if the LTC2174 ADC is
14-bit, the data of each channel is stored in a 16-bit word. Along the
datapath, we call *sample* a 64-bit vector containing a sample for
each channel. At the output of the ADC core, a flow control FIFO
allows to cope with the memory controller temporary unavailabilities
(due to DDR refresh cycles).
.. figure:: ../fig/adc_core_sys_clk.svg
:alt: Acquisition logic diagram (system clock domain)
Acquisition logic diagram (system clock domain).
Samples are stored interleaved in the DDR memory. `Figure
6.2 <#fig_003amem_005fsamples>`__ illustrates the way samples are
written, stored and read in the DDR memory. The DDR memory size is 2Gb
or 256MB.
This means that the maximum number of samples that can be stored is 128M (\ *2^{27}*16*).
.. figure:: ../fig/memory_samples.svg
:alt: Illustration of samples storage in DDR memory
Illustration of samples storage in DDR memory.
The acquisition process is driven by a state machine. At
start-up (system reset), the state machine is ``IDLE``, waiting for an
acquisition start command (``ACQ_START``). Commands are sent to the
state machine by writing in the ``FSM_CMD`` field of the control
register (see `ADC Core Registers <#ADC-Core-Registers>`__).
.. figure:: ../fig/acq_fsm.svg
:alt: Acquisition state machine
Acquisition state machine.
When a start command is received, the state machine goes to ``PRE_TRIG``
and stays in this state until the programmed number of pre-trigger
samples are recorded. After that, it goes in ``WAIT_TRIG`` state and
continue recording sample to memory. If the number of programmed
pre-trigger samples is zero, the state machine skips the ``PRE_TRIG``
state and it foes directly to ``WAIT_TRIG``. When a valid trigger is
detected, the state machine moves to ``POST_TRIG``. It will stay in this
state until the programmed number of post-trigger samples is reached.
The next state is ``TRIG_TAG`` where the trigger time-tag (4x 32-bit
word) is pushed after the last post-trigger sample (to be stored in DDR
memory). When the trigger time-tag has been pushed (two clock cycles),
the state machine goes to ``DECR_SHOT``. From ``DECR_SHOT`` it either
goes back to ``IDLE`` if the number of shots is reached or it repeats
the same cycle for the next shot.
When the acquisition is finished (state machine back to ``IDLE``) and
all samples have been written to the DDR memory, only then the software
can retrieve the samples using DMA transfer. An interrupt is generated
when the acquisition ends.
.. note::
Start commands are taken into account only in ``IDLE`` state.
.. note::
Triggers are taken into account only in ``WAIT_TRIG`` state.
.. note::
A stop command will bring the state machine back to ``IDLE`` from any state.
.. note::
After a stop command, no end of acquisition interrupt is generated.
There are two LEDs on the fmc-adc front panel. The LED labeled ``ACQ``
is turned ON when the acquisition state machine is **not** in the
``IDLE`` state. The LED labeled ``TRIG`` flashes when a valid trigger is
detected **and** the acquisition state machine is in the ``WAIT_TRIG``
state.
.. note::
The number of pre-trigger sample can be zero, but there **must** be
at least one post-trigger sample.
.. note::
In addition to the requested pre/post-trigger samples, an
additional sample, corresponding to the trigger, will be recorded.
.. note::
The start of an acquisition is prohibited if either the number of
shots or the number of post-trigger samples is equal to zero.
Single-shot Mode
~~~~~~~~~~~~~~~~
The procedure below lists the different steps of a single-shot
acquisition process.
#. Configure acquisition (trigger, number of samples, interrupts, etc...).
#. Issue a start acquisition command (the acquisition state machine must
be ``IDLE``).
#. When a valid trigger is detected, an interrupt is generated (if enabled).
#. At the end of the acquisition, another interrupt is generated.
#. Read trigger position register.
#. Configure the DMA to retrieve data.
#. Start the DMA transfer (the acquisition state machine must be ``IDLE``).
#. When the DMA transfer is done, an interrupt is generated.
#. The board is ready for a new acquisition start command.
In single-shot mode, the DDR memory is used as a circular buffer. When
the acquisition starts, samples are directly written to the DDR memory
(via FIFOs). The acquisition logic stops writing to the memory when the
configured number of pre/post-trigger samples is reached. It could
happen that the write pointer reaches the top of the memory before the
end of the acquisition. In this case, the write pointer is reset to
address zero and overwrites previous samples. In order to allow the
software to retrieve the requested samples (around the trigger), the
*Trigger address* register stores the write pointer address at the
trigger moment.
.. note::
The value stored in the *Trigger address* register is a byte address.
.. note::
Every new acquisition starts writing at address ``0x0``.
The following two figures illustrate the use of the DDR memory as a
circular buffer. The acquisition state machine is also represented.
.. figure:: ../fig/memory_single-shot.svg
:alt: Single-shot mode acquisition example
Single-shot mode acquisition example.
.. figure:: ../fig/memory_single-shot_overlap.svg
:alt: Single-shot mode acquisition example (overlapping DDR memory)
Single-shot mode acquisition example (overlapping DDR memory).
.. note::
*Orange*: Samples written to memory and read back via DMA.
*Grey*: Samples written to memory, but not read. *White*: Empty memory
(or previous acquisition samples).
Multi-shot Mode
~~~~~~~~~~~~~~~
The multi-shot acquisition process is almost identical to the
single-shot one, except that once the acquisition is started it will go
around the state machine as many times as the number of configured
shots. This means that if the board is configured for N shots, it will
generate N trigger interrupts (if enabled) and then another interrupt at
the end of the acquisition. A counter, accessible via a register, shows
the remaining number of shots (see `ADC Core
Registers <#ADC-Core-Registers>`__).
Unlike the single-mode acquisition, in multi-shot, the DDR memory is not
used as a circular buffer. Instead, two dual port RAM (dpram) are
implemented inside the FPGA. Those dprams are alternatively used as
circular buffer for each shot. Even shots use dpram0 and odd shots
dpram1.
When a shot is finished, the corresponding dpram samples are written to
the DDR memory. Only the pre-trigger samples, the post-trigger samples
and the trigger time-tag are written. The first shot is written starting
at address ``0x0``. Then the second shot is written right after the
trigger time-tag of the first shot. The following figure shows the
shots organisation in the DDR memory.
.. figure:: ../fig/memory_multi-shot.svg
:alt: DDR memory usage in multi-shot mode acquisition.
DDR memory usage in multi-shot mode acquisition.
.. note::
The number of samples per shot stored in memory is equal to:
number of pre-trigger samples + number of post-trigger samples + 1
(trigger sample) + 2 (time-tag).
.. note::
In multi-shot mode, the start of an acquisition is prohibited
if the number of sample per shot is bigger or equal to the dpram size.
.. note::
The size of the dprams is configurable during the generation
of the FPGA bitstream (VHDL generic), but not at runtime. The software
can retrieve the maximum *allowed* value from the *Multi-shot sample
depth register* (see `ADC Core Registers <#ADC-Core-Registers>`__). The
value stored in that read-only register already takes into account the 2
samples reserved for the time-tag (eg. if the actual maximum number of
samples allowed is 8000, the register will read 7998).
Calibration Data Storage in EEPROM
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following table describes the ADC calibration arrangement.
+-----------------+-----------------+-----------------+-----------------+
| Byte offset | Input range | Description | Type |
+=================+=================+=================+=================+
| 0x00 | 10V | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x02 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x04 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x06 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x08 | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x0A | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x0C | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x0E | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x10 | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
| 0x12 | 1V | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x14 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x16 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x18 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x1A | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x1C | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x1E | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x20 | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x22 | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
| 0x24 | 100mV | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x26 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x28 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x2A | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x2C | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x2E | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x30 | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x32 | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x34 | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
The following table describes the DAC calibration arrangement.
+-----------------+-----------------+-----------------+-----------------+
| Byte offset | Input range | Description | Type |
+=================+=================+=================+=================+
| 0x36 | 10V | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x38 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x3A | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x3C | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x3E | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x40 | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x42 | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x44 | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x46 | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
| 0x48 | 1V | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x4A | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x4C | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x4E | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x50 | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x52 | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x54 | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x56 | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x58 | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
| 0x5A | 100mV | Offset | 16-bit signed |
| | | correction | |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x5C | | Offset | 16-bit signed |
| | | correction | |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x5E | | Offset | 16-bit signed |
| | | correction | |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x60 | | Offset | 16-bit signed |
| | | correction | |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x62 | | Gain correction | 16-bit unsigned |
| | | channel 1 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x64 | | Gain correction | 16-bit unsigned |
| | | channel 2 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x66 | | Gain correction | 16-bit unsigned |
| | | channel 3 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x68 | | Gain correction | 16-bit unsigned |
| | | channel 4 | |
+-----------------+-----------------+-----------------+-----------------+
| 0x6A | | Temperature | 16-bit unsigned |
| | | | \* 0.01° |
+-----------------+-----------------+-----------------+-----------------+
Glossary
========
**Local bus**
The **local bus** is the interface between the GN4124 and the FPGA.
**Pulse**
In this document, a **pulse** refers to a one clock tick wide pulse.
**Tick**
A clock **tick** corresponds to a period of the clock.
**VIC**
Vectored Interrupt Controller
**EIC**
Embedded Interrupt Controller
.. _`HDL Make`: http://www.ohwr.org/projects/hdl-make
.. _`OpenCores Wishbone`: http://opencores.org/opencores,wishbone
.. _`OpenCores`: http://opencores.org/
.. _`GN4124`: PCI Express bridge from Semtech (formerly Gennum)
.. _`24AA64`: http://ww1.microchip.com/downloads/en/devicedoc/21189f.pdf
.. _`Xilinx CoreGen`: http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
.. _`LTC2174`: https://www.analog.com/media/en/technical-documentation/data-sheets/21754314fa.pdf
.. _`MAX5441-MAX5444`: http://datasheets.maximintegrated.com/en/ds/MAX5441-MAX5444.pdf
.. _`OpenCores SPI`: http://opencores.org/project,spi
.. _`OpenCores Onewire`: http://opencores.org/project,sockit_owm
.. _`Si570`: https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
.. _`OpenCores I2C`: http://opencores.org/project,i2c
.. _`Platform Management FRU Information Storage Definition v1.0`:
.. _`General Cores`: http://www.ohwr.org/projects/general-cores
.. _`DDR3 SP6 core`: http://www.ohwr.org/hdl-core-lib/ddr3-sp6-core
.. _`GN4124 core`: http://www.ohwr.org/hdl-core-lib/gn4124-core
.. _`VME64x Slave`: http://www.ohwr.org/hdl-core-lib/vme64x-core
.. _`SPEC`: https://ohwr.org/project/spec
.. _`SVEC`: https://ohwr.org/project/svec
doc/gateware/memory-map.rst 0 → 100644
View file @ f8b05f5d
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
==============
The Memory Map
==============
Following the memory map for the part of the ADC design that drives
the FMC ADC 100M modules.
.. raw:: html
:file: regs/fmc_adc_mezzanine_mmap.htm
Supported Designs
=================
Here you can find the complete memory MAP for the supported
designs. This will include the ADC register as well as the carrier
registers and any other component used in an FMC ADC 100M design.
.. toctree::
:maxdepth: 1
:caption: Table of Contents
spec_ref_fmc_adc_100M
svec_ref_fmc_adc_100M
doc/manual/regs/Makefile → doc/gateware/regs/Makefile
View file @ f8b05f5d
SOURCES = $(wildcard *.cheby)
SOURCES = $(wildcard *.cheby) ../../../hdl/cheby/fmc_adc_mezzanine_mmap.cheby
TARGETS = $(SOURCES:.cheby=.htm)
all: $(TARGETS)
......@@ -6,10 +6,8 @@ all: $(TARGETS)
.PHONY: $(TARGETS) clean
$(TARGETS): %.htm : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-doc=$@ --doc html
# @cheby -i $< --gen-doc=$(@:.htm=.rst) --doc rest
# @cheby -i $< --gen-doc=$(@:.htm=.md) --doc md
@echo -e "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-doc=$(shell basename $@) --doc html
clean:
@rm -f *.md *.rst *.htm
doc/gateware/spec_ref_fmc_adc_100M.rst 0 → 100644
View file @ f8b05f5d
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
=================
SPEC FMC ADC 100M
=================
.. raw:: html
:file: regs/spec_ref_fmc_adc_100Ms_doc.htm
doc/gateware/svec_ref_fmc_adc_100M.rst 0 → 100644
View file @ f8b05f5d
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2020 CERN
=================
SVEC FMC ADC 100M
=================
.. raw:: html
:file: regs/svec_ref_fmc_adc_100Ms_doc.htm
doc/index.rst
View file @ f8b05f5d
......@@ -13,3 +13,4 @@ FMC-ADC-100M-14B-4CHA documentation
introduction
software/index
gateware/index
gateware/memory-map
doc/manual/Makefile deleted 100644 → 0
View file @ f2640a29
#
# Makefile for the documentation directory
#
# Copyright 1994,2000,2010,2011 Alessandro Rubini <rubini@linux.it>
#
#################
# There is not basenames here, all *.in are considered input
INPUT = $(wildcard *.in)
TEXI = $(INPUT:.in=.texi)
INFO = $(INPUT:.in=.info)
HTML = $(INPUT:.in=.html)
TXT = $(INPUT:.in=.txt)
PDF = $(INPUT:.in=.pdf)
ALL = $(INFO) $(HTML) $(TXT) $(PDF)
MAKEINFO ?= makeinfo
%.texi: %.in
@rm -f $@
sed -f ./infofilter $< > $@
emacs -batch --no-site-file -l fixinfo $@
chmod -w $@
%.pdf: %.texi
texi2pdf --batch $<
%.info: %.texi
$(MAKEINFO) $< -o $@
%.html: %.texi
$(MAKEINFO) --html --no-split -o $@ $<
%.txt: %.texi
$(MAKEINFO) --no-headers $< > $@
##############################################
.PHONY: all images check terse clean install
.INTERMEDIATE: $(TEXI)
all: images $(ALL)
$(MAKE) terse
images::
if [ -d images ]; then $(MAKE) -C images || exit 1; fi
check: _err.ps
gs -sDEVICE=linux -r320x200x16 $<
terse:
for n in cp fn ky pg toc tp vr aux log; do rm -f *.$$n; done
rm -f *~
clean: terse
rm -f $(ALL) $(TEXI)
# add the other unused targets, so the rule in ../Makefile works
modules install modules_install:
doc/manual/fixinfo deleted 100644 → 0
View file @ f2640a29
;; use:
;; emacs -batch -l ./fixinfo.el <file>
;; or, better:
;; emacs -batch --no-site-file -l ./fixinfo.el <file>
(defun fixinfo (file)
(find-file-other-window file)
(message (concat "Maxing texinfo tree in " file))
(texinfo-all-menus-update)
(texinfo-every-node-update)
(save-buffer)
(kill-buffer (current-buffer))
)
;; loop over command line arguments
(mapcar 'fixinfo command-line-args-left)
(kill-emacs)
doc/manual/fmc_adc_100Ms_csr.tex deleted 100644 → 0
View file @ f2640a29
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{ctl} @tab
Control register
@item @code{0x4} @tab
REG @tab
@code{sta} @tab
Status register
@item @code{0x8} @tab
REG @tab
@code{trig_stat} @tab
Trigger status
@item @code{0xc} @tab
REG @tab
@code{trig_en} @tab
Trigger enable
@item @code{0x10} @tab
REG @tab
@code{trig_pol} @tab
Trigger polarity
@item @code{0x14} @tab
REG @tab
@code{ext_trig_dly} @tab
External trigger delay
@item @code{0x18} @tab
REG @tab
@code{sw_trig} @tab
Software trigger
@item @code{0x1c} @tab
REG @tab
@code{shots} @tab
Number of shots
@item @code{0x20} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
@item @code{0x24} @tab
REG @tab
@code{shots_cnt} @tab
Remaining shots counter
@item @code{0x28} @tab
REG @tab
@code{trig_pos} @tab
Trigger address register
@item @code{0x2c} @tab
REG @tab
@code{fs_freq} @tab
Sampling clock frequency
@item @code{0x30} @tab
REG @tab
@code{sr} @tab
Sample rate
@item @code{0x34} @tab
REG @tab
@code{pre_samples} @tab
Pre-trigger samples
@item @code{0x38} @tab
REG @tab
@code{post_samples} @tab
Post-trigger samples
@item @code{0x3c} @tab
REG @tab
@code{samples_cnt} @tab
Samples counter
@item @code{0x80} @tab
REG @tab
@code{ch1_ctl} @tab
Channel 1 control register
@item @code{0x84} @tab
REG @tab
@code{ch1_sta} @tab
Channel 1 status register
@item @code{0x88} @tab
REG @tab
@code{ch1_gain} @tab
Channel 1 gain calibration register
@item @code{0x8c} @tab
REG @tab
@code{ch1_offset} @tab
Channel 1 offset calibration register
@item @code{0x90} @tab
REG @tab
@code{ch1_sat} @tab
Channel 1 saturation register
@item @code{0x94} @tab
REG @tab
@code{ch1_trig_thres} @tab
Channel 1 trigger threshold configuration register
@item @code{0x98} @tab
REG @tab
@code{ch1_trig_dly} @tab
Channel 1 trigger delay
@item @code{0x100} @tab
REG @tab
@code{ch2_ctl} @tab
Channel 2 control register
@item @code{0x104} @tab
REG @tab
@code{ch2_sta} @tab
Channel 2 status register
@item @code{0x108} @tab
REG @tab
@code{ch2_gain} @tab
Channel 2 gain calibration register
@item @code{0x10c} @tab
REG @tab
@code{ch2_offset} @tab
Channel 2 offset calibration register
@item @code{0x110} @tab
REG @tab
@code{ch2_sat} @tab
Channel 2 saturation register
@item @code{0x114} @tab
REG @tab
@code{ch2_trig_thres} @tab
Channel 2 trigger threshold configuration register
@item @code{0x118} @tab
REG @tab
@code{ch2_trig_dly} @tab
Channel 2 trigger delay
@item @code{0x180} @tab
REG @tab
@code{ch3_ctl} @tab
Channel 3 control register
@item @code{0x184} @tab
REG @tab
@code{ch3_sta} @tab
Channel 3 status register
@item @code{0x188} @tab
REG @tab
@code{ch3_gain} @tab
Channel 3 gain calibration register
@item @code{0x18c} @tab
REG @tab
@code{ch3_offset} @tab
Channel 3 offset calibration register
@item @code{0x190} @tab
REG @tab
@code{ch3_sat} @tab
Channel 3 saturation register
@item @code{0x194} @tab
REG @tab
@code{ch3_trig_thres} @tab
Channel 3 trigger threshold configuration register
@item @code{0x198} @tab
REG @tab
@code{ch3_trig_dly} @tab
Channel 3 trigger delay
@item @code{0x200} @tab
REG @tab
@code{ch4_ctl} @tab
Channel 4 control register
@item @code{0x204} @tab
REG @tab
@code{ch4_sta} @tab
Channel 4 status register
@item @code{0x208} @tab
REG @tab
@code{ch4_gain} @tab
Channel 4 gain calibration register
@item @code{0x20c} @tab
REG @tab
@code{ch4_offset} @tab
Channel 4 offset calibration register
@item @code{0x210} @tab
REG @tab
@code{ch4_sat} @tab
Channel 4 saturation register
@item @code{0x214} @tab
REG @tab
@code{ch4_trig_thres} @tab
Channel 4 trigger threshold configuration register
@item @code{0x218} @tab
REG @tab
@code{ch4_trig_dly} @tab
Channel 4 trigger delay
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{1...0}
@tab R/W @tab
@code{FSM_CMD}
@tab @code{0} @tab
State machine commands (ignore on read)
@item @code{2}
@tab R/W @tab
@code{FMC_CLK_OE}
@tab @code{0} @tab
FMC Si750 output enable
@item @code{3}
@tab R/W @tab
@code{OFFSET_DAC_CLR_N}
@tab @code{0} @tab
Offset DACs clear (active low)
@item @code{4}
@tab W/O @tab
@code{MAN_BITSLIP}
@tab @code{0} @tab
Manual serdes bitslip (ignore on read)
@item @code{5}
@tab R/W @tab
@code{TEST_DATA_EN}
@tab @code{0} @tab
Enable test data
@item @code{6}
@tab R/W @tab
@code{TRIG_LED}
@tab @code{0} @tab
Manual TRIG LED
@item @code{7}
@tab R/W @tab
@code{ACQ_LED}
@tab @code{0} @tab
Manual ACQ LED
@item @code{8}
@tab W/O @tab
@code{CLEAR_TRIG_STAT}
@tab @code{0} @tab
Clear trigger status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fsm_cmd} @tab 1: ACQ_START (start acquisition, only when FSM is idle)@*2: ACQ_STOP (stop acquisition, anytime)
@item @code{test_data_en} @tab Write the DDR RAM address counter value instead of ADC data to DDR.@*Note that no timetags are appended at the end of test data.
@item @code{trig_led} @tab Manual control of the front panel TRIG LED
@item @code{acq_led} @tab Manual control of the front panel ACQ LED
@item @code{clear_trig_stat} @tab Write 1 to clear the last trigger status register. Auto-resets to zero.
@end multitable
@regsection @code{sta} - Status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{2...0}
@tab R/O @tab
@code{FSM}
@tab @code{X} @tab
State machine status
@item @code{3}
@tab R/O @tab
@code{SERDES_PLL}
@tab @code{X} @tab
SerDes PLL status
@item @code{4}
@tab R/O @tab
@code{SERDES_SYNCED}
@tab @code{X} @tab
SerDes synchronization status
@item @code{5}
@tab R/O @tab
@code{ACQ_CFG}
@tab @code{X} @tab
Acquisition configuration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: TRIG_TAG@*6: DECR_SHOT@*7: illegal
@item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked
@item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{} Shot number > 0@*@bullet{} Post-trigger sample > 0
@end multitable
@regsection @code{trig_stat} - Trigger status
Shows the source(s) of the last received trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{EXT}
@tab @code{X} @tab
External trigger input
@item @code{1}
@tab R/O @tab
@code{SW}
@tab @code{X} @tab
Software trigger
@item @code{4}
@tab R/O @tab
@code{TIME}
@tab @code{X} @tab
Timetag trigger
@item @code{8}
@tab R/O @tab
@code{CH1}
@tab @code{X} @tab
Channel 1 internal threshold trigger
@item @code{9}
@tab R/O @tab
@code{CH2}
@tab @code{X} @tab
Channel 2 internal threshold trigger
@item @code{10}
@tab R/O @tab
@code{CH3}
@tab @code{X} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/O @tab
@code{CH4}
@tab @code{X} @tab
Channel 4 internal threshold trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext} @tab 0: not triggered@*1: triggered
@item @code{sw} @tab 0: not triggered@*1: triggered
@item @code{time} @tab 0: not triggered@*1: triggered
@item @code{ch1} @tab 0: not triggered@*1: triggered
@item @code{ch2} @tab 0: not triggered@*1: triggered
@item @code{ch3} @tab 0: not triggered@*1: triggered
@item @code{ch4} @tab 0: not triggered@*1: triggered
@end multitable
@regsection @code{trig_en} - Trigger enable
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{EXT}
@tab @code{0} @tab
External trigger input
@item @code{1}
@tab R/W @tab
@code{SW}
@tab @code{0} @tab
Software trigger
@item @code{4}
@tab R/W @tab
@code{TIME}
@tab @code{0} @tab
Timetag trigger
@item @code{5}
@tab R/W @tab
@code{ALT_TIME}
@tab @code{0} @tab
Alternate timetag trigger
@item @code{8}
@tab R/W @tab
@code{CH1}
@tab @code{0} @tab
Channel 1 internal threshold trigger
@item @code{9}
@tab R/W @tab
@code{CH2}
@tab @code{0} @tab
Channel 2 internal threshold trigger
@item @code{10}
@tab R/W @tab
@code{CH3}
@tab @code{0} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/W @tab
@code{CH4}
@tab @code{0} @tab
Channel 4 internal threshold trigger
@item @code{16}
@tab R/W @tab
@code{FWD_EXT}
@tab @code{0} @tab
Forward external trigger to trigger out
@item @code{24}
@tab R/W @tab
@code{FWD_CH1}
@tab @code{0} @tab
Forward channel 1 internal threshold trigger to trigger out
@item @code{25}
@tab R/W @tab
@code{FWD_CH2}
@tab @code{0} @tab
Forward channel 2 internal threshold trigger to trigger out
@item @code{26}
@tab R/W @tab
@code{FWD_CH3}
@tab @code{0} @tab
Forward channel 3 internal threshold trigger to trigger out
@item @code{27}
@tab R/W @tab
@code{FWD_CH4}
@tab @code{0} @tab
Forward channel 4 internal threshold trigger to trigger out
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext} @tab 0: disable@*1: enable
@item @code{sw} @tab 0: disable@*1: enable
@item @code{time} @tab 0: disable@*1: enable
@item @code{alt_time} @tab 0: disable@*1: enable
@item @code{ch1} @tab 0: disable@*1: enable
@item @code{ch2} @tab 0: disable@*1: enable
@item @code{ch3} @tab 0: disable@*1: enable
@item @code{ch4} @tab 0: disable@*1: enable
@item @code{fwd_ext} @tab 0: disable@*1: enable
@item @code{fwd_ch1} @tab 0: disable@*1: enable
@item @code{fwd_ch2} @tab 0: disable@*1: enable
@item @code{fwd_ch3} @tab 0: disable@*1: enable
@item @code{fwd_ch4} @tab 0: disable@*1: enable
@end multitable
@regsection @code{trig_pol} - Trigger polarity
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{EXT}
@tab @code{0} @tab
External trigger input
@item @code{8}
@tab R/W @tab
@code{CH1}
@tab @code{0} @tab
Channel 1 internal threshold trigger
@item @code{9}
@tab R/W @tab
@code{CH2}
@tab @code{0} @tab
Channel 2 internal threshold trigger
@item @code{10}
@tab R/W @tab
@code{CH3}
@tab @code{0} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/W @tab
@code{CH4}
@tab @code{0} @tab
Channel 4 internal threshold trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch1} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch2} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch3} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch4} @tab 0: positive edge/slope@*1: negative edge/slope
@end multitable
@regsection @code{ext_trig_dly} - External trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{EXT_TRIG_DLY}
@tab @code{0} @tab
External trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{sw_trig} - Software trigger
Writing (anything) to this register generates a software trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SW_TRIG}
@tab @code{0} @tab
Software trigger (ignore on read)
@end multitable
@regsection @code{shots} - Number of shots
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{NB}
@tab @code{0} @tab
Number of shots
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{nb} @tab Number of shots required in multi-shot mode, set to one for single-shot mode.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{MULTI_DEPTH}
@tab @code{X} @tab
Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
@end multitable
@regsection @code{shots_cnt} - Remaining shots counter
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/O @tab
@code{VAL}
@tab @code{X} @tab
Remaining shots counter
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Counts the number of remaining shots to acquire.
@end multitable
@regsection @code{trig_pos} - Trigger address register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{TRIG_POS}
@tab @code{X} @tab
Trigger address
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pos} @tab Trigger address in DDR memory.@*Only used in single-shot mode.
@end multitable
@regsection @code{fs_freq} - Sampling clock frequency
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{FS_FREQ}
@tab @code{X} @tab
Sampling clock frequency
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fs_freq} @tab ADC sampling clock frequency in Hz
@end multitable
@regsection @code{sr} - Sample rate
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{UNDERSAMPLE}
@tab @code{0} @tab
Undersampling ratio
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{undersample} @tab Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).
@end multitable
@regsection @code{pre_samples} - Pre-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{PRE_SAMPLES}
@tab @code{0} @tab
Pre-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pre_samples} @tab Number of requested pre-trigger samples (>1).
@end multitable
@regsection @code{post_samples} - Post-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{POST_SAMPLES}
@tab @code{0} @tab
Post-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{post_samples} @tab Number of requested post-trigger samples (>1).
@end multitable
@regsection @code{samples_cnt} - Samples counter
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{SAMPLES_CNT}
@tab @code{X} @tab
Samples counter
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{samples_cnt} @tab Counts the number of samples.@* It is reset on START and then counts the number of pre-trigger + post-trigger samples
@end multitable
@regsection @code{ch1_ctl} - Channel 1 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 1
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@end multitable
@regsection @code{ch1_sta} - Channel 1 status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/O @tab
@code{VAL}
@tab @code{X} @tab
Channel 1 current ADC value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@end multitable
@regsection @code{ch1_gain} - Channel 1 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 1
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@end multitable
@regsection @code{ch1_offset} - Channel 1 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 1
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@end multitable
@regsection @code{ch1_sat} - Channel 1 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{14...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 1
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch1_trig_thres} - Channel 1 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{HYST}
@tab @code{0} @tab
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis.@*The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
@end multitable
@regsection @code{ch1_trig_dly} - Channel 1 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH1_TRIG_DLY}
@tab @code{0} @tab
Channel 1 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch1_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 2
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@end multitable
@regsection @code{ch2_sta} - Channel 2 status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/O @tab
@code{VAL}
@tab @code{X} @tab
Channel 2 current ACD value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@end multitable
@regsection @code{ch2_gain} - Channel 2 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 2
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@end multitable
@regsection @code{ch2_offset} - Channel 2 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 2
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@end multitable
@regsection @code{ch2_sat} - Channel 2 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{14...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 2
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch2_trig_thres} - Channel 2 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{HYST}
@tab @code{0} @tab
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis.@*The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
@end multitable
@regsection @code{ch2_trig_dly} - Channel 2 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH2_TRIG_DLY}
@tab @code{0} @tab
Channel 2 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch2_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 3
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@end multitable
@regsection @code{ch3_sta} - Channel 3 status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/O @tab
@code{VAL}
@tab @code{X} @tab
Channel 3 current ADC value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@end multitable
@regsection @code{ch3_gain} - Channel 3 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 3
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@end multitable
@regsection @code{ch3_offset} - Channel 3 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 3
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@end multitable
@regsection @code{ch3_sat} - Channel 3 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{14...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 3
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch3_trig_thres} - Channel 3 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{HYST}
@tab @code{0} @tab
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis.@*The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
@end multitable
@regsection @code{ch3_trig_dly} - Channel 3 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH3_TRIG_DLY}
@tab @code{0} @tab
Channel 3 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch3_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{0} @tab
Solid state relays control for channel 4
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ssr} @tab Controls input voltage range, termination and DC offset error calibration@*0x23: 100mV range@*0x11: 1V range@*0x45: 10V range@*0x00: Open input@*0x42: 100mV range calibration@*0x40: 1V range calibration@*0x44: 10V range calibration@*Bit3 is indepandant of the others and enables the 50ohms termination.
@end multitable
@regsection @code{ch4_sta} - Channel 4 status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/O @tab
@code{VAL}
@tab @code{X} @tab
Channel 4 current ADC value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Current ADC raw value. The format is binary two's complement.
@end multitable
@regsection @code{ch4_gain} - Channel 4 gain calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Gain calibration for channel 4
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Gain applied to all data coming from the ADC.@*Fixed point format:@*Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
@end multitable
@regsection @code{ch4_offset} - Channel 4 offset calibration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Offset calibration for channel 4
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@end multitable
@regsection @code{ch4_sat} - Channel 4 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{14...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Saturation value for channel 4
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch4_trig_thres} - Channel 4 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{0} @tab
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{HYST}
@tab @code{0} @tab
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis.@*The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
@end multitable
@regsection @code{ch4_trig_dly} - Channel 4 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH4_TRIG_DLY}
@tab @code{0} @tab
Channel 4 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch4_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: disable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: disable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{TRIG}
@tab @code{0} @tab
Trigger interrupt
@item @code{1}
@tab W/O @tab
@code{ACQ_END}
@tab @code{0} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab write 1: enable interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab write 1: enable interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/O @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is enabled@*read 0: interrupt 'Trigger interrupt' is disabled
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is enabled@*read 0: interrupt 'End of acquisition interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG}
@tab @code{X} @tab
Trigger interrupt
@item @code{1}
@tab R/W @tab
@code{ACQ_END}
@tab @code{X} @tab
End of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig} @tab read 1: interrupt 'Trigger interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'Trigger interrupt'@*write 0: no effect
@item @code{acq_end} @tab read 1: interrupt 'End of acquisition interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'End of acquisition interrupt'@*write 0: no effect
@end multitable
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\input texinfo @c -*-texinfo-*-
%
% fmcadc100m14b4cha_firmware_manual.in - main file for the documentation
%
%%%%
%------------------------------------------------------------------------------
%
% NOTE FOR THE UNAWARE USER
% =========================
%
% This file is a texinfo source. It isn't the binary file of some strange
% editor of mine. If you want ASCII, you should "make fmcadc100m14b4cha_firmware_manual.txt".
%
%------------------------------------------------------------------------------
%
% This is not a conventional info file...
% I use three extra features:
% - The '%' as a comment marker, if at beginning of line ("\%" -> "%")
% - leading blanks are allowed (this is something I can't live without)
% - braces are automatically escaped when they appear in example blocks
%
@comment %**start of header
@documentlanguage en
@documentencoding UTF-8
@setfilename fmcadc100m14b4cha_firmware_manual.info
@settitle fmcadc100m14b4cha_firmware_manual
@iftex
@afourpaper
@end iftex
@c @paragraphindent 0
@comment %**end of header
@setchapternewpage off
@set update-month April 2016
@finalout
@titlepage
@title FmcAdc100m14b4cha Gateware Guide
@subtitle @value{update-month} - Release 4.1
@subtitle For PCIe (SPEC) and VME64x (SVEC) FMC Carriers
@image{../fig/ohr_logo,5cm,,,pdf}
@sp 10
@flushright
@image{../fig/cern_logo,3cm,,,pdf}
@end flushright
@author Matthieu Cattin (CERN)
@author Dimitrios Lampridis (CERN)
@end titlepage
@headings single
@iftex
@contents
@end iftex
@c ##########################################################################
@node Top
@top Introduction
This document describes the gateware developed to support the FmcAdc100m14b4cha (later refered to as fmc-adc) mezzanine card on the SPEC@footnote{@uref{http://www.ohwr.org/projects/spec}} and SVEC@footnote{@uref{http://www.ohwr.org/projects/svec}} carrier cards.
The gateware is the HDL code used to generate the bitstream that configures the FPGA on the carrier (sometimes also called firmware).
The gateware architecture is described in detail.
The configuration and operation of the fmc-adc is also explained.
On the other hand, this manual is not intended to provide information about the software used to control the fmc-adc board, nor details about it's hardware design.
@c ##########################################################################
@node Repositories and Releases
@chapter Repositories and Releases
This project is hosted on the Open Hardware Repository, at the following link:@*
@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw}
Here a list of resources that you can find on the project page.
@table @code
@item Documents@footnote{@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/documents}}
contains the @t{.bin} FPGA binary files and the @t{.pdf} documentation for every official release.
@item Repository@footnote{@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository}}
contains the git repository of the project.
@end table
On the repository the official releases have a tag named
@code{spec-fmc-adc-v#maj.#min} (or @code{svec-fmc-adc-v#maj.#min}) where @code{#maj} represent the major release
version of the gateware and @code{#min} the minor one (e.g @code{spec-fmc-adc-v1.2}).
The released FPGA binary files follow the same naming convention.
The git commit hash has to be written in the sdb meta-information, therefore a release consists of two commits.
The commit coming right after the tagged one contains the updated sdb meta-information file, the ise project and the synthesis, place&route, timing, and the reports.
@b{Note:} If you got this from the repository (as opposed to a named @i{tar.gz} or @i{pdf} file) it may happen that you are looking at a later commit than the release this manual claims to document.
It is a fact of life that developers forget to re-read and fix documentation while updating the code. In that case, please run ``@code{git describe HEAD}'' to ensure where you are.
@c ==========================================================================
@section Software Support
For information on the fmc-adc Linux software support, please refer to the following project:@*
@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-sw}
As a general rule, a new minor version of the gateware, for a given major version, should be backwards compatible.
If the interface with the driver changes, the major version should be incremented.
This means that driver versions 1.x should work with any gateware version 1.x.
But the driver version 2.0 might not work with the gateware version 1.1.
@c ##########################################################################
@page
@node About source code
@chapter About Source Code
@c ==========================================================================
@section Build from Sources
The fmc-adc hdl design make use of the @command{hdlmake}@footnote{@uref{http://www.ohwr.org/projects/hdl-make}} tool.
It automatically fetches the required hdl cores and libraries. It also generates Makefiles for synthesis/par and simulation.
Here is the procedure to build the FPGA binary image from the hdl source.
@enumerate
@item Install @command{hdlmake} (version 2.1).
@item Get fmc-adc hdl sources.@*
@code{git clone git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha-gw.git <src_dir>}
@item Goto the synthesis directory.@*
@code{cd <src_dir>/hdl/<carrier>/syn/}
@item Fetch the dependencies and generate a synthesis Makefile.@*
@code{hdlmake}
@item Perform synthesis, place, route and generate FPGA bitstream.@*
@code{make}
@end enumerate
@c TODO explain how to fetch dependencies with git submodules.
@c TODO explain how to build without hdlmake.
@c ==========================================================================
@section Source Code Organisation
@table @file
@item hdl/adc/rtl/
ADC specific hdl sources.
@item hdl/adc/wb_gen/
ADC specific @command{wbgen2} sources, html documentation and C header file.
@item hdl/ip_cores/
Location of fetched and generated hdl cores and libraries.
@item hdl/<carrier>/rtl/
Carrier related hdl sources.
@item hdl/<carrier>/wb_gen/
Carrier related @command{wbgen2} sources, html documentation and C header file.
@item hdl/<carrier>/syn/
Synthesis directory for selected carrier. This is where the synthesis top manifest and the ISE project are stored.
For each release, the synthesis, place&route and timing reports are also saved here.
@item hdl/<carrier>/sim/
@item hdl/<carrier>/testbench/
Carrier related simulation files and testbenches.
@item hdl/<carrier>/chipscope/
Carrier related Chipscope projects used for debug purpose.
@end table
It could happen that a hdl source directory contains extra source files that are not used in the current gateware release.
In order to identify the source files used in a given release, refer to the @file{Manifest.py} files.
@c ==========================================================================
@section Dependencies
The fmc-adc gateware depends on the following hdl cores and libraries:
@table @b
@item general-cores
@code{repo : git://ohwr.org/hdl-core-lib/general-cores.git}@*
@code{commit: c26ee857158e4a65fd9d2add8b63fcb6fb4691ea}
@item ddr3-sp6-core
@code{repo : git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git}@*
@code{commit: e4d6755cc9c9c5cb005ce12eb82b12552922b882}
@item gn4124-core (spec carrier only)
@code{repo : git://ohwr.org/hdl-core-lib/gn4124-core.git}@*
@code{commit: e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab}
@item vme64x-core (svec carrier only)
@code{repo : git://ohwr.org/hdl-core-lib/vme64x-core.git}@*
@code{commit: b2fc3ce76485404f831d15f7ce31fdde08e234d5}
@end table
@c ##########################################################################
@page
@node Architecture
@chapter Architecture
This chapter describes the internal blocks of the FPGA for both SPEC (PCIe) and SVEC (VME64x) carriers.
The gateware is designed around one or several Wishbone@footnote{@uref{http://opencores.org/opencores@comma{}wishbone}} bus interconnects.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
@c ==========================================================================
@section SPEC (PCIe carrier)
In the PCIe version of the gateware, all blocks (except the memory controller) are connected to the PCIe bridge interface using the same Wishbone bus (@i{main} bus).
The ADC samples are written and read to/from the DDR memory using separate Wishbone bus interconnects.
Due to its size, the DDR memory is not mapped on the @i{main} Wishbone bus and can only be accessed through DMA.
@ref{fig:spec_fw_arch} illustrates the fmc-adc gateware architecture on the SPEC carrier.
A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space.
@float Figure,fig:spec_fw_arch
@center @image{../fig/spec_fw_arch, 15cm,,,pdf}
@caption{FMC-ADC gateware architecture on SPEC carrier.}
@end float
@sp 1
There are three different Wishbone bus interconnects in the design.
@table @b
@item Mapped WB bus (blue)
This bus connects all the peripherals to the GN4142 core.@*
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
@item ADC core to memory controller (orange)
This bus is used to write samples from the ADC core to the DDR memory.@*
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
@item Memory controller to GN4124 core (red)
This bus is used to read samples from the DDR memory.@*
Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
@end table
@ref{tab:spec_memory_map} shows the Wishbone slaves mapping and hierarchy.
The first column represents the byte address offset from the start of the Wishbone address space (BAR 0).
@float Table,tab:spec_memory_map
@include spec_wb_tree.txt
@caption{Wishbone bus memory mapping (BAR 0).}
@end float
@ignore
@float Table,tab:memory_map
@multitable {Byte offset}{xwb_onewire_master}{fmc-adc-100m14b4cha}{Mezzanine system I2C master}
@headitem Byte offset @tab Core @tab Library @tab Description
@item @code{0x0000} @tab sdb_rom @tab general-cores @tab SDB records
@item @code{0x1000} @tab gn4124_core @tab gn4124-core @tab DMA controller
@item @code{0x1100} @tab xwb_onewire_master @tab general-cores @tab Carrier 1-wire master
@item @code{0x1200} @tab carrier_csr @tab fmc-adc-100m14b4cha @tab Carrier control and status
@item @code{0x1300} @tab irq_controller @tab fmc-adc-100m14b4cha @tab Interrupt controller
@item @code{0x2000} @tab utc_core @tab fmc-adc-100m14b4cha @tab Time-tagging core
@item @code{0x4000} @tab sdb_rom @tab general-cores @tab fmc-adc bridge SDB records
@item @code{0x5000} @tab xwb_i2c_master @tab general-cores @tab Mezzanine system I2C master
@item @code{0x5100} @tab xwb_spi @tab general-cores @tab Mezzanine SPI master
@item @code{0x5200} @tab xwb_i2c_master @tab general-cores @tab Mezzanine I2C master
@item @code{0x5300} @tab fmc_adc_100Ms_core @tab fmc-adc-100m14b4cha @tab ADC core
@item @code{0x5400} @tab xwb_onewire_master @tab general-cores @tab Mezzanine 1-wire master
@end multitable
@caption{Wishbone bus memory mapping (BAR 0).}
@end float
@end ignore
@sp 1
The Wishbone crossbar also implements SDB@footnote{@uref{http://www.ohwr.org/projects/fpga-config-space}} records. Those records describe the Wishbone slaves and their mapping on the bus.
The SDB records ROM must be located at offset @code{0x0}.
In order to identify the gateware, SDB meta-information records are used.
The 'Integration', 'Top module repository url' and 'Synthesis tool information' meta-information records are used in the design.
Below is a description of the fields and their content in the fmc-adc design on the SPEC carrier.
@table @b
@item Integration
vendor_id = 0x0000CE42 (CERN vendor ID)@*
device_id = 0x47C786A2 (echo "spec_fmc-adc-100m14b4cha"|md5sum|cut -c1-8) @*
version = [31:16]=major, [15:0]=minor, bcd encoded@*
date = bcd encoded release date, format yyyymmdd@*
name = "spec_fmcadc100m14b"
@item Top module repository url
repo_url = "fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"@*
@i{(This is not the full URL, it lacks the "git://ohwr.org/" prefix due to the 63-byte limitation of the field.)}
@item Synthesis tool information
syn_module_name = "spec_top_fmc_adc"@*
syn_commit_id = git log -1 --format="%H" | cut -c1-32 @*
syn_tool_name = "ISE"@*
syn_tool_version = bcd encoded synthesis tool version@*
syn_date = bcd encoded synthesis date, format yyyymmdd@*
syn_username = username of person who synthesised the design
@end table
Note that some of the cores from the general-cores library are based on cores from
OpenCores@footnote{@uref{http://opencores.org/}}. Therefore, the documentation for those cores is hosted on the OpenCores website.
@c --------------------------------------------------------------------------
@subsection Clock Domains
The SPEC version of the fmc-adc design has five different clock domains. They are listed in the following table.
@float
@multitable {@code{sys_clk_125}}{ADC data de-serialiser clock}{125.00 MHz}{400MHz LTC2174 (mezzanine)}
@headitem Name @tab Description @tab Frequency @tab Source
@item @code{sys_clk_125} @tab Main system clock @tab 125.00 MHz @tab 20MHz TCXO (carrier)
@item @code{ddr_clk} @tab DDR interface clock @tab 333.33 MHz @tab 20MHz TCXO (carrier)
@item @code{fs_clk} @tab Sampling clock @tab 100.00 MHz @tab 400MHz LTC2174 (mezzanine)
@item @code{serdes_clk} @tab ADC data de-serialiser clock @tab 800.00 MHz @tab 400MHz LTC2174 (mezzanine)
@item @code{p2l_clk} @tab Local bus clock @tab 200.00 MHz @tab 200MHz GN4124 (carrier)
@end multitable
@end float
@sp 1
@c --------------------------------------------------------------------------
@subsection GN4124 Core
This block is the interface between the GN4124@footnote{PCI Express bridge from Semtech (formerly Gennum)} local bus and the other blocks in the FPGA.
The GN4124 is a four lane PCI Express Generation 1.1 bridge. In addition to the PHY, it also contains the data link and transaction layers.
The GN4124 bridge is used to access the FPGA registers, but also to generate MSI interrupts and re-program the FPGA.
BAR4 (Base Address Register) allows access to the GN4124 internal registers.
BAR0 is connected to the local bus and therefore allows access to the FPGA.
The GN4124 core is made of a local bus interface with the GN4124 chip, a Wishbone bus master mapped to BAR0 and a DMA controller. The DMA controller has two Wishbone ports, a Wishbone slave to configure the DMA controller and a Wishbone master.
In the fmc-adc gateware, the master port is connected to the DDR memory controller.
The GN4124 Wishbone interfaces (masters and slave) are 32-bit data width and 32-bit word aligned addresses.
@b{Note:} It would not be beneficial to insert an address converter (for non-interleaved data read) between the GN4124 core and the memory controller, because the DDR memory access is not efficient when reading non-consecutive addresses.
@c --------------------------------------------------------------------------
@subsection DMA Embedded Interrupt Controller (EIC)
The DMA EIC gathers the interrupts from the GN4124 DMA controller.
There are two inputs to the DMA EIC:
@itemize @textdegree
@item @b{DMA done}: This interrupt signals the end of a DMA transfer.
@item @b{DMA error}: This interrupt signals an error in a DMA transfer.
@end itemize
The two inputs are multiplexed and the result is forwarded to the VIC (@ref{Vectored Interrupt Controller (VIC)}).
Interrupt sources can be masked using the enable and disable registers.
An interrupt is cleared by writing a one to the corresponding bit of the status register.
The registers description can be found in annex @ref{DMA Embedded Interrupt Controller Registers}).
@c --------------------------------------------------------------------------
@subsection SPEC Carrier Control and Status Registers
This block contains control and status registers related to the SPEC carrier board.
A first register allows to readout the carrier PCB revision and carrier type.
Another register signals the presence of a mezzanine in the FMC slot, gives the status of the local bus and system PLLs and indicates the DDR memory controller calibration state.
The last register of this block allows to control the two carrier's LEDs on the front panel.
@b{Note:} The ``Carrier Type'' field is used only for test purpose. The carrier board identification is done through the PCI Express vendor and device ID.
The registers description can be found in annex @ref{SPEC Carrier Registers}.
@c ==========================================================================
@section SVEC (VME64x carrier)
In the VME64x version of the gateware, all blocks are connected to the VME64x core using a single Wishbone bus. Here the DDR memory is not accessed through DMA, but using a indirect addressing scheme explained later in @ref{DDR Memory Controller}.
A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space.
@float Figure,fig:svec_fw_arch
@center @image{../fig/svec_fw_arch, 15cm,,,pdf}
@caption{FMC-ADC gateware architecture on SVEC carrier.}
@end float
@sp 1
There are three different Wishbone bus interconnects in the design.
@table @b
@item Mapped WB bus (blue)
This bus connects all the peripheral to the VME64x core.@*
Data: 32-bit, address: 32-bit (word aligned),@*
Clock: system clock (125MHz) and system clock / 2 (62.5MHz), see note below.
@item ADC cores to memory controllers (2x, orange)
These two buses are used to write samples from the ADC cores to the DDR memories.@*
Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
@end table
@b{Note:} The VME64x core cannot work with a clock frequency as high as 125MHz, therefore it is clocked with half the system clock frequency.
As the fmc-adc core needs 125MHz to work properly, a Wishbone clock crossing component is inserted between the VME64x core and the first Wishbone crossbar component.
With this topology, only the VME64x core runs at a lower frequency.
@ref{tab:svec_memory_map} shows the Wishbone slaves mapping and hierarchy.
The first column represents the byte address offset from the start of the Wishbone address space.
@float Table,tab:svec_memory_map
@include svec_wb_tree.txt
@caption{Wishbone bus memory mapping.}
@end float
@sp 1
Same as in the SPEC version, SDB meta-information records are used to identify the gateware.
Below is a description of the fields and their content in the fmc-adc design on SVEC carrier.
@table @b
@item Integration
vendor_id = 0x0000CE42 (CERN vendor ID)@*
device_id = 0x47C786A2 (echo "svec_fmc-adc-100m14b4cha"|md5sum|cut -c1-8) @*
version = [31:16]=major, [15:0]=minor, bcd encoded@*
date = bcd encoded release date, format yyyymmdd@*
name = "svec_fmcadc100m14b"
@item Top module repository url
repo_url = "fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"@*
@i{(This is not the full URL, it lacks the "git://ohwr.org/" prefix due to the 63-byte limitation of the field.)}
@item Synthesis tool information
syn_module_name = "svec_top_fmc_adc"@*
syn_commit_id = git log -1 --format="%H" | cut -c1-32 @*
syn_tool_name = "ISE"@*
syn_tool_version = bcd encoded synthesis tool version@*
syn_date = bcd encoded synthesis date, format yyyymmdd@*
syn_username = username of person who synthesised the design
@end table
@c --------------------------------------------------------------------------
@subsection Clock Domains
The SPEC version of the fmc-adc design has five different clock domains. They are listed in the following table.
@float
@multitable {@code{sys_clk_62_5}}{ADC data de-serialiser clock}{125.00 MHz}{400MHz LTC2174 (mezzanine)}
@headitem Name @tab Description @tab Frequency @tab Source
@item @code{sys_clk_125} @tab Main system clock @tab 125.00 MHz @tab 20MHz TCXO (carrier)
@item @code{sys_clk_62_5} @tab System clock / 2@tab 62.50 MHz @tab 20MHz TCXO (carrier)
@item @code{ddr_clk} @tab DDR interface clock @tab 333.33 MHz @tab 20MHz TCXO (carrier)
@item @code{fs_clk} @tab Sampling clock @tab 100.00 MHz @tab 400MHz LTC2174 (mezzanine)
@item @code{serdes_clk} @tab ADC data de-serialiser clock @tab 800.00 MHz @tab 400MHz LTC2174 (mezzanine)
@end multitable
@end float
@sp 1
@c --------------------------------------------------------------------------
@subsection VME64x Core
The VME64x core implements a VME slave on one side and a Wishbone pipelined master on the other side.
For more information about the VME64x core, visit the OHWR page@footnote{@uref{http://www.ohwr.org/projects/vme64x-core}}.
@c --------------------------------------------------------------------------
@subsection SVEC Carrier Control and Status
This block contains control and status registers related to the SVEC carrier board.
The registers description can be found in annex (@ref{SVEC Carrier Registers}).
@c --------------------------------------------------------------------------
@subsection SVEC Carrier I2C Master
The I2C master accesses the 24AA64 64Kb EEPROM memory chip@footnote{@uref{http://ww1.microchip.com/downloads/en/devicedoc/21189f.pdf}} located on the SVEC board.
This memory is useful to store board specific data (e.g. MAC address, White Rabbit calibration data).
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}i2c}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
@multitable @columnfractions .20 .50
@headitem I2C slave address @tab Peripheral
@item @code{0x51} @tab 24AA64 64Kb EEPROM memory
@end multitable
@sp 1
This block is clocked by the system clock (125 MHz).
Therefore for a SCL clock of 100 kHz, the prescaler configuration is @code{PRESCALER=249}.
@example
@group
PRESCALER = f_sys / (5 * f_scl) - 1
@end group
@end example
@c ==========================================================================
@section Common Cores
@c --------------------------------------------------------------------------
@subsection Carrier 1-wire Master
This 1-wire master controls the DS18B20 thermometer chip located on the carrier board.
This chip also contains a unique 64-bit identifier.
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}sockit_owm}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
This block is clocked by the system clock (125 MHz).
Therefore the dividers configuration are @code{CDR_N=624} and @code{CDR_O=124}.
@example
@group
CDR_N = f_sys * 5E-6 - 1
CDR_O = f_sys * 1E-6 - 1
@end group
@end example
@c --------------------------------------------------------------------------
@node DDR Memory Controller
@subsection DDR Memory Controller
The memory controller block is the interface between the 256MB DDR3 memory located on the carrier boards and the other blocks in the FPGA.
It is basically a MCB core (Memory Controller Block) generated with Xilinx CoreGen@footnote{@uref{http://www.xilinx.com/support/documentation/user_guides/ug388.pdf}} and an additional wrapper implementing two Wishbone slave interfaces@footnote{@uref{http://www.ohwr.org/projects/ddr3-sp6-core}}.
One of the Wishbone slave interfaces is connected to the ADC core.
In the SPEC gateware, the other Wishbone slave interface is connected to the DMA Wishbone master of the GN4124 core.
In the SVEC gateware, the other slave Wishbone interface is connected to an indirect addressing block.
This block consists of an address pointer register and a data FIFO.
To access the DDR memory, the gateware sets the address pointer and then reads/writes data using the FIFO.
On each access to the FIFO, the address pointer is automatically incremented.
@float
@multitable {WB Slave}{Description}{Data width}{Access type}
@headitem WB Slave @tab Description @tab Data width @tab Access type
@item @code{0} @tab ADC core @tab 64-bit @tab Write only
@item @code{1} @tab host side @tab 32-bit @tab Read/write
@sp 1
@end multitable
@end float
The memory controller side connected to the chip is 16-bit wide, clocked at 333.33 MHz DDR.
This gives a maximum bandwidth of 1333.33 MB/s.
Each of the four ADC channels requires 200 MB/s (16-bits per sample, 100 MHz), for a total of 800 MB/s.
In the current design, the two Wishbone ports have the same priority and the arbitration is done with a simple round-robin.
Therefore, samples stored in the DDR memory should not be read during an acquisition.
@c --------------------------------------------------------------------------
@node Vectored Interrupt Controller (VIC)
@subsection Vectored Interrupt Controller (VIC)
In order to redirect interrupts from different cores to the corresponding driver in the Linux kernel in a generic way, a two layers scheme is used.
The first layer is the Embedded Interrupt Controllers (EIC) in each core multiplexing interrupt sources to a single line.
The second layer is the Vectored Interrupt Controller (VIC) multiplexing the interrupt lines from the EICs into a single line to the host.
The VIC keeps a table, initialized with the base addresses of the EICs connected to each of the input.
Note that the VIC configuration is different between the SPEC and SVEC carriers.
The SPEC uses an edge sensitive scheme while the SVEC uses a level sensitive scheme.
@table @b
@item SPEC, VIC control register:
enable = 1@*
polarity = 1@*
emulate edge sensitive = 1@*
edge emulation pulse = 750
@item SVEC, VIC control register:
enable = 1@*
polarity = 1@*
@end table
@b{Note:} On the SPEC carrier, the VIC interrupt request output is connected to GPIO 8 of the GN4124 chip.
Therefore, the GN4124 must be configured to generate an MSI when a rising edge is detected on GPIO 8.
The registers description can be found in annex @ref{Vectored Interrupt Controller}).
@c ==========================================================================
@section FMC-ADC Core
The ADC core is the main block of the design.
On the mezzanine interface side, it takes a data flow from the LTC2174 ADC chip, an external trigger and controls the analogue switches to select the input range or calibration mode.
On the internal interface side, it has a Wishbone master to write data to the DDR memory controller.
It also has a Wishbone slave to access the internal components.
The internal detailed functioning of this block is described further in the document (@xref{Configuration}, @ref{Calibration} and @ref{Acquisition}).
@c --------------------------------------------------------------------------
@subsection Sampling clock
The sampling frequency is determined by a Si570 programmable oscillator located on the fmc-adc mezzanine.
By default, the sampling clock is 100MHz (oscillator factor default value), but it can be changed to any frequency from 10MHz to 105MHz. The lower bound is defined by the Si570 oscillator while the upper bound is limited by the LTC2174 ADC itself.
The Si570 clock output is connected to the LTC2174 ADC.
Then the data clock (DCO) output of the LTC2174 is connected to the FPGA.
The data clock is four times the sampling clock.
The sampling clock (@code{fs_clk}) and the ADC data de-serialiser clock (@code{serdes_clk}) are derived from the data clock using a PLL (internal to the FPGA).
@b{Note:} The internal PLL expects a 400MHz input frequency (define in the hdl code), therefore the sampling frequency has to be 100MHz and can't be changed dynamically.
@c TODO : possibility to control the Si570 via I2C
The ADC core implements a sampling clock frequency meter.
The measured frequency (in Hz) can be read via a register (@pxref{ADC Core Registers}).
@c --------------------------------------------------------------------------
@subsection Time-tagging Core
This block allows time-tagging of important events in the ADC core.
It is based on two free-running counters;
a seconds counter and a 125MHz system clock ticks counter.
The system clock ticks counter is also called coarse counter.
These two counters are accessible in read/write via a Wishbone interface.
For example, the host computer can use the OS time to set the seconds counter and simply reset the coarse counter.
It is planned, in a later release, to set the time-tagging core counters using the White Rabbit core.
A time-tag is made of four 32-bit words; meta-data, seconds, coarse, fine.
The fine field is always set to zero and the meta-data register does not contain useful information, only random data for debugging purposes.
The following events are time-tagged:
@itemize @textdegree
@item Trigger
@item Acquisition start
@item Acquisition stop
@item Acquisition end
@end itemize
@b{Note:} The trigger time tag corresponds to the moment when the acquisition state machine leaves the @code{WAIT_TRIG} state.
@b{Note:} The trigger time-tag is also stored in the data memory, after the post-trigger samples.
This allows to always have a trigger time-tag, even in multi-shot mode (retrieving the time-tag using the trigger interrupt was not fast enough in certain cases).
@b{Note:} If during an acquisition no stop command is issued (normal case), the acquisition stop time-tag is not updated.
The register description can be found in annex @ref{Time-tagging Core Registers}.
@c --------------------------------------------------------------------------
@subsection FMC-ADC Control and Status Registers
This block contains control and status registers related to the fmc-adc core.
The registers description can be found in annex (@ref{ADC Core Registers}).
@c --------------------------------------------------------------------------
@subsection Mezzanine SPI Master
This SPI master controls the LTC2174 ADC@footnote{@uref{http://cds.linear.com/docs/en/datasheet/21754314fa.pdf}} and the four MAX5442 offset DACs@footnote{@uref{http://datasheets.maximintegrated.com/en/ds/MAX5441-MAX5444.pdf}}.
The following table shows how the peripherals are wired to the core.
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}spi}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
@multitable @columnfractions .20 .35
@headitem SPI slave select @tab Peripheral
@item @code{0} @tab LTC2174 ADC
@item @code{1} @tab MAX5442 DAC for channel 1
@item @code{2} @tab MAX5442 DAC for channel 2
@item @code{3} @tab MAX5442 DAC for channel 3
@item @code{4} @tab MAX5442 DAC for channel 4
@end multitable
@sp 1
This block is clocked by the system clock (125 MHz).
Therefore for a SCLK of ~620 kHz, the divider configuration is @code{DIVIDER=100}.
@example
@group
f_sclk = f_sys / ((DIVIDER+1) * 2)
@end group
@end example
@c --------------------------------------------------------------------------
@subsection Mezzanine 1-wire Master
This 1-wire master controls the DS18B20 thermometer chip located on the mezzanine board.
This chip also contains a unique 64-bit identifier.
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}sockit_owm}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
This block is clocked by the system clock (125 MHz).
Therefore the dividers configuration are @code{CDR_N=624} and @code{CDR_O=124}.
@c --------------------------------------------------------------------------
@subsection Mezzanine I2C Master
This I2C master controls the Si570 programmable oscillator chip@footnote{@uref{https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf}} located on the mezzanine board.
This chip is used to produce the ADC sampling clock.
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}i2c}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
@multitable @columnfractions .20 .50
@headitem I2C slave address @tab Peripheral
@item @code{0x55} @tab Si570 programmable oscillator
@end multitable
@sp 1
This block is clocked by the system clock (125 MHz).
Therefore for a SCL clock of 100 kHz, the prescaler configuration is @code{PRESCALER=249}.
@example
@group
PRESCALER = f_sys / (5 * f_scl) - 1
@end group
@end example
@c --------------------------------------------------------------------------
@subsection Mezzanine System Management I2C Master
This I2C master accesses the 24AA64 64Kb EEPROM memory chip@footnote{@uref{http://ww1.microchip.com/downloads/en/devicedoc/21189f.pdf}} located on the mezzanine board.
This memory is mandatory as specified in the FMC standard (VITA 57.1). It is connected to the system management I2C bus, also specified in the FMC standard.
This block is based on an OpenCores design@footnote{@uref{http://opencores.org/project@comma{}i2c}}.
@c FIXME broken @comma{} to generate url link (prints 'comma{}' instead of ',')
@multitable @columnfractions .20 .50
@headitem I2C slave address @tab Peripheral
@item @code{0x50} @tab 24AA64 64Kb EEPROM memory
@end multitable
@sp 1
This block is clocked by the system clock (125 MHz).
Therefore for a SCL clock of 100 kHz, the prescaler configuration is @code{PRESCALER=249}.
@example
@group
PRESCALER = f_sys / (5 * f_scl) - 1
@end group
@end example
@c --------------------------------------------------------------------------
@subsection FMC-ADC Embedded Interrupt Controller (EIC)
The fmc-adc EIC gathers the interrupts from the ADC core.
There are two inputs to the fmc-adc EIC:
@itemize @textdegree
@item @b{Trigger}: This interrupt signals that a valid trigger arrived while the acquisition state machine was in the @code{WAIT_TRIG} state.
@item @b{Acquisition end}: This interrupt signals the end of an acquisition. In case of multi-shot acquisition, it occurs at the end of the last shot.
@end itemize
The two inputs are multiplexed and the result is forwarded to the VIC (@ref{Vectored Interrupt Controller (VIC)}).
Interrupt sources can be masked using the enable and disable registers.
An interrupt is cleared by writing a one to the corresponding bit of the status register.
The registers description can be found in annex @ref{FMC-ADC Embedded Interrupt Controller Registers}).
@c ##########################################################################
@page
@node Configuration
@chapter Configuration
@ref{fig:adc_core_fs_clk} is a block diagram of the ADC core part in the sampling clock domain. It contains an ADC data stream de-serialiser, an offset and gain correction block (for ADC data), an under-sampling block and a trigger unit.
The four channels' data and the trigger signal are synchronised to the system clock domain using a FIFO.
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (@command{wbgen2} feature).
@float Figure,fig:adc_core_fs_clk
@center @image{../fig/adc_core_fs_clk, 14cm,,,pdf}
@caption{ADC core diagram (sampling clock domain).}
@end float
The LTC2174 is by default configured in @i{2-Lane Output Mode, 16-Bit Serialization}.
In the fmc-adc application, this default configuration is kept.
@ref{fig:ltc2174_mode} is an extract from the LTC2174 datasheet illustrating the @i{2-Lane Output Mode, 16-Bit Serialization} waveforms.
@float Figure,fig:ltc2174_mode
@center @image{../fig/ltc2174_mode, 12cm,,,pdf}
@caption{LTC2174 data output mode waveforms.}
@end float
There are two 800Mbit/s lanes per ADC channel.
Eight data lanes in total and the frame rate (FR) lane are fed to a de-serialiser in the FPGA.
The frame rate signal is used to align the de-serialiser to data words.
The four channel data (16-bit) are concatenated together to form a 64-bit vector.
As shown in @ref{fig:ltc2174_mode}, the two LSB bits of a data word are always set to zero.
@strong{Important:} Upon reset the ADC defaults to ``offset binary''
representation for the channel data. However, the ADC core expects
``two's complement''. Therefore, it is important to change the
relevant configuration register in the ADC itself. When using the
provided FMC-ADC driver, this is done automatically during driver
initialisation.
@c ==========================================================================
@section Control and Status Registers
Writing one to to the @code{FMC_CLK_OE} field of the ADC core control register enables the sampling clock (Si570 chip).
Also, in order to use the input offset DACs, the @code{OFFSET_DAC_CLR_N} field must be set to one.
The field @code{MAN_BITSLIP} allows to 'manually' control the ADC data alignment in the de-serialiser.
When @code{TEST_DATA_EN} is set, the ADC core writes the address pointer to the memory instead of the ADC samples.
The fields @code{TRIG_LED} and @code{ACQ_LED} allows to control the FMC front panel LEDs.
Those four fields are for test purpose only and must stay zero in normal operation.
When the sampling clock is enabled, the @code{SERDES_PLL} and @code{SERDES_SYNCED} field from the ADC core status register must be set to one.
@c ==========================================================================
@section Input Ranges
@ref{fig:analogue_input} shows a simplified schematic diagram of the analogue input stage used for each channel.
Each input can be independently configured with one of the three available ranges; 100mV, 1V, 10V.
Each range is defined as the maximum peak-to-peak input voltage.
Independently to the selected range, a 50ohms termination can be added to each input.
In addition to the three ranges for normal operation, there are three more configurations used for offset calibration of each range.
Opto-isolated analogue switches are used to apply the various configurations. They are represented by standard switch symbols in the simplified schematic.
@float Figure,fig:analogue_input
@center @image{../fig/analogue_input, 10cm,,,pdf}
@caption{Simplified schematic diagram of the analogue input stage.}
@end float
Only the following input switch configurations are valid.
For all others switch configurations, the behavior is not defined and therefore shouldn't be used.
@float Table,tab:switch_config
@multitable {SW[7..1]}{SW7}{SW6}{SW5}{SW4}{SW3}{SW2}{SW1}{100mV range offset calibration}
@headitem SW[7..1] @tab SW7 @tab SW6 @tab SW5 @tab SW4 @tab SW3 @tab SW2 @tab SW1 @tab Description
@item @code{0x23} @tab @code{OFF} @tab @code{ON} @tab @code{OFF} @tab @code{X} @tab @code{OFF} @tab @code{ON} @tab @code{ON} @tab 100mV range
@item @code{0x11} @tab @code{OFF} @tab @code{OFF} @tab @code{ON} @tab @code{X} @tab @code{OFF} @tab @code{OFF} @tab @code{ON} @tab 1V range
@item @code{0x45} @tab @code{ON} @tab @code{OFF} @tab @code{OFF} @tab @code{X} @tab @code{ON} @tab @code{OFF} @tab @code{ON} @tab 10V range
@item @code{0x42} @tab @code{ON} @tab @code{OFF} @tab @code{OFF} @tab @code{X} @tab @code{OFF} @tab @code{ON} @tab @code{OFF} @tab 100mV range offset calibration
@item @code{0x40} @tab @code{ON} @tab @code{OFF} @tab @code{OFF} @tab @code{X} @tab @code{OFF} @tab @code{OFF} @tab @code{OFF} @tab 1V range offset calibration
@item @code{0x44} @tab @code{ON} @tab @code{OFF} @tab @code{OFF} @tab @code{X} @tab @code{ON} @tab @code{OFF} @tab @code{OFF} @tab 10V range offset calibration
@item @code{0x00} @tab @code{X} @tab @code{OFF} @tab @code{OFF} @tab @code{OFF} @tab @code{X} @tab @code{X} @tab @code{OFF} @tab Input disconnected
@item @code{0x08} @tab @code{X} @tab @code{X} @tab @code{X} @tab @code{ON} @tab @code{X} @tab @code{X} @tab @code{X} @tab 50ohm termination
@end multitable
@caption{Analogue input switches configurations.}
@end float
@c ==========================================================================
@section Input Offset
Each channel has a 16-bit DAC allowing to apply a dc offset to the input signal.
The voltage range of the DAC is 10V (-5V to +5V) and is independent from the selected input range.
The following equation shows how to convert a digital value written to a DAC to an offset voltage.
@example
@group
v_dac = (v_ref * d_dac/0x8000) - v_ref
Where:
v_ref = DAC's voltage reference = 5V
d_dac = Digital value written to the DAC
v_dac = DAC voltage
Example:
0xFFFF => 4.999V
0x8000 => 0.000V
0x0000 => -5.000V
@end group
@end example
The following equation shows the relation between the input voltage and the offset (applied by the DAC).
Note that the offset from the DAC is subtracted from the input voltage.
@example
@group
v_out = v_in - v_dac
Where:
v_in = Input voltage
v_dac = DAC voltage
v_out = Output voltage (to filter and ADC)
@end group
@end example
@c ==========================================================================
@section Trigger
The trigger unit is made of two hardware and one software sources.
The hardware and software paths can be enabled independently.
The two paths are then or'ed together to drive a delay generator.
The delay generator allows to insert a predefined number of sampling clock periods before the trigger is forwarded to the acquisition state machine.
@ref{fig:trig_unit} shows a simplified digram of the trigger unit.
@float Figure,fig:trig_unit
@center @image{../fig/trigger_unit, 12cm,,,pdf}
@caption{Trigger unit diagram.}
@end float
The hardware trigger source can be either internal (based on an ADC input channel) or external (dedicated trigger input).
For both internal and external hardware triggers, the polarity can be selected between positive and negative slope (resp. rising and falling edge).
By default the polarity is set to positive slope.
The external trigger input is synchronised to the sampling clock.
The external trigger pulse must be at least one sampling clock cycle wide.
To use the internal trigger source, both the ADC input channel and the threshold should be configured.
By default, channel 1 is selected and the threshold is set to 0.
Note that the threshold is 16-bit signed (two's complement).
@ref{fig:trig_hw_int} sketches the internal hardware trigger threshold behavior.
@float Figure,fig:trig_hw_int
@center @image{../fig/trig_hw_int, 8cm,,,pdf}
@caption{Internal hardware trigger threshold.}
@end float
Furthermore, a glitch filter can be applied to the threshold detection.
The glitch filter is useful to trigger on noisy signals.
In order to help setting the glitch filter, an internal trigger test mode can be activated.
When the test mode is enabled, data from channels 2, 3 and 4 is replaced as follow:
@multitable @columnfractions .12 .50
@item Channel 2 @tab Input signal over threshold
@item Channel 3 @tab Input signal over threshold filtered
@item Channel 4 @tab Trigger
@end multitable
@sp 1
The software trigger source consists of a pulse generated when a write cycle is detected on the @i{Software trigger} register. For further information on the trigger configuration registers @pxref{ADC Core Registers}.
@c ==========================================================================
@section Undersampling
The undersampling block is simply validating one in N samples and forwarding it to the acquisition logic.
The number (N) is configured in the @i{Sample rate} register.
If N > 1, then the trigger pulse is aligned to the next valid sample.
If N = 1 all the samples are valid and therefore the trigger is always aligned.
A value of N = 0 is treated as N = 1 in the gateware.
@c ##########################################################################
@page
@node Calibration
@chapter Calibration
Calibration is done once during the production tests.
It can be repeated afterwards with the production test suite (PTS) and the corresponding testbench.
The calibration process gives the following four values per channel and per input range:
@itemize @textdegree
@item ADC gain correction
@item ADC offset correction
@item DAC gain correction
@item DAC offset correction
@end itemize
Note that the temperature during the calibration process is also measured.
This could be used for later temperature compensated calibration value computing.
@c ==========================================================================
@section Calibration data storage
All the calibration values are stored in the FmcAdc100m14b4cha EEPROM.
The EEPROM holds an sdbfs@footnote{@uref{http://www.ohwr.org/attachments/download/1594/sdbfs-2012-09-19.pdf}} file system.
In addition to the calibration values, the EEPROM also contains mandatory IPMI@footnote{Platform Management FRU Information Storage Definition v1.0} records specified in the FMC Standard VITA 57.1 (see table @ref{tab:eeprom_sdbfs} for mapping).
@float Table,tab:eeprom_sdbfs
@multitable @columnfractions .12 .18 .15 .30
@headitem Byte offset @tab File name @tab File Type @tab Description
@item @code{0x0} @tab IPMI-FRU @tab binary @tab IPMI records
@item @code{0x100} @tab calib @tab binary @tab Calibration values
@item @code{auto} @tab name @tab ascii @tab Contains "adc_100m"
@item @code{0x800} @tab data @tab binary @tab Empty directory
@item @code{0x200} @tab . @tab binary @tab Root directory
@item @tab @tab @tab vendor = 0xCE42
@item @tab @tab @tab device = 0xC5BE045E
@end multitable
@caption{EEPROM sdb file system.}
@end float
Note that the vendor value 0xCE42 corresponds to CERN. While the device value 0xC5BE045E corresponds to the first 32-bit of the md5 sum of "fmc-adc-100m14b4cha".
@c ==========================================================================
@section Calibration Data Usage
@subsection ADC Calibration
Two registers per channel are implemented in the FPGA for ADC gain and offset correction.
When an input range is selected, the corresponding gain/offset correction values must be loaded from the EEPROM to those registers.
@float Figure,fig:off_gain_corr
@center @image{../fig/offset_gain_corr, 12cm,,,pdf}
@caption{ADC offset and gain correction block.}
@end float
The offset register takes a 16-bit signed value.
The gain register takes a 16-bit fixed point value.
The fixed point format is as follow:
@float Figure,fig:adc_gain_format
@center @image{../fig/adc_gain_format, 13cm,,,pdf}
@caption{ADC gain register format.}
@end float
After the offset and gain corrections are applied, the signal is saturated to a user-programmable value.
One register per channel allows to set the saturation value.
The saturation register takes a 15-bit unsigned value.
From this value, two 'symmetrical' 16-bit signed numbers are derived and taken as the saturation boundaries.
@b{Note:} Because the default value (on FPGA start-up) is not configurable in wbgen2, the gain, offset and saturation registers are set to 0x0 at start-up.
Therefore, the driver has to initialise those registers.
@b{Note:} After gain and offset correction, the two LSB of the data words can be different from zero.
@b{Note:} It is usually the driver's task to read the calibration data from the FMC EEPROM and load them to the corresponding registers. This has to be done once at start-up and then every time the input range is changed.
@subsection DAC Calibration
The DAC value is only set once before an acquisition.
Therefore, there is no need to implement the gain and offset correction in the FPGA.
The software controlling the fmc-adc must apply the DAC gain and offset correction prior to writing a value to the DAC.
As for the ADC correction values, there is one pair (offset, gain) of DAC correction values per input range.
Below is the formula to calculate the corrected DAC value (applying gain and offset correction):
@example
@group
c_val = ((val + offset) * gain/0x8000) + 0x8000
where:
c_val = corrected value to write to DAC (16-bit unsigned)
val = value from user (16-bit signed)
offset = DAC offset calibration value from EEPROM (16-bit signed)
gain = DAC gain calibration value from EEPROM (16-bit fixed point)
@end group
@end example
@c ##########################################################################
@page
@node Acquisition
@chapter Acquisition
This chapter describes the two modes of acquisition, single-shot and multi-shot.
It also explains how the software is expected to control the fmc-adc acquisitions.
@ref{fig:adc_core_sys_clk} shows the ADC core acquisition logic.
The heart of the acquisition logic is a state machine driven by user commands (start, stop), the trigger signal and counters events (e.g. pre-trig done, etc...).
The ADC samples are routed along a datapath (bold arrows), which depends on the acquisition mode.
It is explained in detail in the @ref{Single-shot Mode} and @ref{Multi-shot Mode}.
The four channels data and the trigger are concatenated together and fed to a FIFO to be synchronised between the sampling clock domain and the system clock domain.
Even if the LTC2174 ADC is 14-bit, the data of each channel is stored in a 16-bit word.
Along the datapath, we call @i{sample} a 64-bit vector containing a sample for each channel.
At the output of the ADC core, a flow control FIFO allows to cope with the memory controller temporary unavailabilities (due to DDR refresh cycles).
@float Figure,fig:adc_core_sys_clk
@center @image{../fig/adc_core_sys_clk, 15cm,,,pdf}
@caption{Acquisition logic diagram (system clock domain).}
@end float
Samples are stored interleaved in the DDR memory.
@ref{fig:mem_samples} illustrates the way samples are written, stored and read in the DDR memory.
The DDR memory size is 2Gb or 256MB.
@w{This means that the maximum number of samples that can be stored is 128M (@math{2^{27}*16}).}
@float Figure,fig:mem_samples
@center @image{../fig/memory_samples, 15cm,,,pdf}
@caption{Illustration of samples storage in DDR memory.}
@end float
The acquisition process is driven by a state machine.
@ref{fig:acq_fsm} represents its states and transitions.
At start-up (system reset), the state machine is @code{IDLE}, waiting for an acquisition start command (@code{ACQ_START}).
Commands are sent to the state machine by writing in the @code{FSM_CMD} field of the control register (@pxref{ADC Core Registers}).
When a start command is received, the state machine goes to @code{PRE_TRIG} and stays in this state until the programmed number of pre-trigger samples are recorded.
After that, it goes in @code{WAIT_TRIG} state and continue recording sample to memory.
If the number of programmed pre-trigger samples is zero, the state machine skips the @code{PRE_TRIG} state and it foes directly to @code{WAIT_TRIG}.
When a valid trigger is detected, the state machine moves to @code{POST_TRIG}.
It will stay in this state until the programmed number of post-trigger samples is reached.
The next state is @code{TRIG_TAG} where the trigger time-tag (4x 32-bit word) is pushed after the last post-trigger sample (to be stored in DDR memory).
When the trigger time-tag has been pushed (two clock cycles), the state machine goes to @code{DECR_SHOT}.
From @code{DECR_SHOT} it either goes back to @code{IDLE} if the number of shots is reached or it repeats the same cycle for the next shot.
When the acquisition is finished (state machine back to @code{IDLE}) and all samples have been written to the DDR memory, only then the software can retrieve the samples using DMA transfer.
An interrupt is generated when the acquisition ends.
@b{Note:} Start commands are taken into account only in @code{IDLE} state.
@b{Note:} Triggers are taken into account only in @code{WAIT_TRIG} state.
@b{Note:} A stop command will bring the state machine back to @code{IDLE} from any state.
@b{Note:} After a stop command, no end of acquisition interrupt is generated.
@float Figure,fig:acq_fsm
@center @image{../fig/acq_fsm, 10cm,,,pdf}
@caption{Acquisition state machine.}
@end float
There are two LEDs on the fmc-adc front panel.
The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b{not} in the @code{IDLE} state.
The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state.
@b{Note:} The number of pre-trigger sample can be zero, but there @b{must} be at least one post-trigger sample.
@b{Note:} In addition to the requested pre/post-trigger samples, an additional sample, corresponding to the trigger, will be recorded.
@b{Note:} The start of an acquisition is prohibited if either the number of shots or the number of post-trigger samples is equal to zero.
@c ==========================================================================
@node Single-shot Mode
@section Single-shot Mode
The procedure below lists the different steps of a single-shot acquisition process.
@enumerate
@item Configure acquisition (trigger, number of samples, interrupts, etc...).
@item Issue a start acquisition command (the acquisition state machine must be @code{IDLE}).
@item When a valid trigger is detected, an interrupt is generated (if enabled).
@item At the end of the acquisition, another interrupt is generated.
@item Read trigger position register.
@item Configure the DMA to retrieve data.
@item Start the DMA transfer (the acquisition state machine must be @code{IDLE}).
@item When the DMA transfer is done, an interrupt is generated.
@item The board is ready for a new acquisition start command.
@end enumerate
In single-shot mode, the DDR memory is used as a circular buffer.
When the acquisition starts, samples are directly written to the DDR memory (via FIFOs).
The acquisition logic stops writing to the memory when the configured number of pre/post-trigger samples is reached.
It could happen that the write pointer reaches the top of the memory before the end of the acquisition.
In this case, the write pointer is reset to address zero and overwrites previous samples.
In order to allow the software to retrieve the requested samples (around the trigger), the @i{Trigger address} register stores the write pointer address at the trigger moment.
@b{Note:} The value stored in the @i{Trigger address} register is a byte address.
@b{Note:} Every new acquisition starts writing at address @code{0x0}.
@ref{fig:mem_single_shot} and @ref{fig:mem_single_shot_overlap} illustrate the use of the DDR memory as a circular buffer.
The acquisition state machine is also represented.
@float Figure,fig:mem_single_shot
@center @image{../fig/memory_single-shot, 15cm,,,pdf}
@caption{Single-shot mode acquisition example.}
@end float
@float Figure,fig:mem_single_shot_overlap
@center @image{../fig/memory_single-shot_overlap, 15cm,,,pdf}
@caption{Single-shot mode acquisition example (overlapping DDR memory).}
@end float
@b{Note:} @i{Orange}: Samples written to memory and read back via DMA.
@i{Grey}: Samples written to memory, but not read.
@i{White}: Empty memory (or previous acquisition samples).
@c ==========================================================================
@node Multi-shot Mode
@section Multi-shot Mode
The multi-shot acquisition process is almost identical to the single-shot one, except that once the acquisition is started it will go around the state machine as many times as the number of configured shots.
This means that if the board is configured for N shots, it will generate N trigger interrupts (if enabled) and then another interrupt at the end of the acquisition.
A counter, accessible via a register, shows the remaining number of shots (@pxref{ADC Core Registers}).
Unlike the single-mode acquisition, in multi-shot, the DDR memory is not used as a circular buffer.
Instead, two dual port RAM (dpram) are implemented inside the FPGA.
Those dprams are alternatively used as circular buffer for each shot.
Even shots use dpram0 and odd shots dpram1.
When a shot is finished, the corresponding dpram samples are written to the DDR memory.
Only the pre-trigger samples, the post-trigger samples and the trigger time-tag are written.
The first shot is written starting at address @code{0x0}.
Then the second shot is written right after the trigger time-tag of the first shot.
@ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
@float Figure,fig:mem_multi_shot
@center @image{../fig/memory_multi-shot, 15cm,,,pdf}
@caption{DDR memory usage in multi-shot mode acquisition.}
@end float
@b{Note:} The number of samples per shot stored in memory is equal to: number of pre-trigger samples + number of post-trigger samples + 1 (trigger sample) + 2 (time-tag).
@b{Note:} In multi-shot mode, the start of an acquisition is prohibited if the number of sample per shot is bigger or equal to the dpram size.
@b{Note:} The size of the dprams is configurable during the generation of the FPGA bitstream (VHDL generic), but not at runtime. The software can retrieve the maximum @i{allowed} value from the @i{Multi-shot sample depth register} (@pxref{ADC Core Registers}). The value stored in that read-only register already takes into account the 2 samples reserved for the time-tag (eg. if the actual maximum number of samples allowed is 8000, the register will read 7998).
@c ##########################################################################
@page
@node Missing Features and Improvements
@chapter Missing Features and Improvements
An up-to-date list of known bugs, missing features and improvements is available in the OHWR project page:@*
@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/issues}
A roadmap for future releases is also available in the OHWR project page:@*
@uref{http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/roadmap}
@c ##########################################################################
@page
@node Appendix
@appendix
@c ==========================================================================
@section Calibration Data Storage in EEPROM
Tables @ref{tab:adc_calibr_data_eeprom} and @ref{tab:dac_calibr_data_eeprom} shows the calibration data types and the arrangement in the binary file.
The first column "Byte offset" represents the offset within the binary file.
@float Table,tab:adc_calibr_data_eeprom
@multitable @columnfractions .10 .10 .35 .40
@headitem Byte offset @tab Input range @tab Description @tab Type
@item @code{0x0} @tab 10V @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x2} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x4} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x6} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x8} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0xA} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0xC} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0xE} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x10} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@item @code{0x12} @tab 1V @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x14} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x16} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x18} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x1A} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0x1C} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0x1E} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0x20} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x22} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@item @code{0x24} @tab 100mV @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x26} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x28} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x2A} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x2C} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0x2E} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0x30} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0x32} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x34} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@end multitable
@caption{ADC calibration data stored in EEPROM (calib file).}
@end float
@float Table,tab:dac_calibr_data_eeprom
@multitable @columnfractions .10 .10 .35 .40
@headitem Byte offset @tab Input range @tab Description @tab Type
@item @code{0x36} @tab 10V @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x38} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x3A} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x3C} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x3E} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0x40} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0x42} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0x44} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x46} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@item @code{0x48} @tab 1V @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x4A} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x4C} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x4E} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x50} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0x52} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0x54} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0x56} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x58} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@item @code{0x5A} @tab 100mV @tab Offset correction channel 1 @tab 16-bit signed
@item @code{0x5C} @tab @tab Offset correction channel 2 @tab 16-bit signed
@item @code{0x5E} @tab @tab Offset correction channel 3 @tab 16-bit signed
@item @code{0x60} @tab @tab Offset correction channel 4 @tab 16-bit signed
@item @code{0x62} @tab @tab Gain correction channel 1 @tab 16-bit unsigned
@item @code{0x64} @tab @tab Gain correction channel 2 @tab 16-bit unsigned
@item @code{0x66} @tab @tab Gain correction channel 3 @tab 16-bit unsigned
@item @code{0x68} @tab @tab Gain correction channel 4 @tab 16-bit unsigned
@item @code{0x6A} @tab @tab Temperature @tab 16-bit unsigned * 0.01@textdegree{}
@end multitable
@caption{DAC calibration data stored in EEPROM (calib file).}
@end float
@c --------------------------------------------------------------------------
@c macro to allow includes from wbgen2 generated tex register documentation
@macro regsection{name}
@section \name\
@end macro
@c --------------------------------------------------------------------------
@page
@appendix ADC Core Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{ADC Core Registers}
@include fmc_adc_100Ms_csr.tex
@c --------------------------------------------------------------------------
@page
@appendix FMC-ADC Embedded Interrupt Controller Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{FMC-ADC Embedded Interrupt Controller Registers}
@include fmc_adc_eic.tex
@c --------------------------------------------------------------------------
@page
@appendix DMA Embedded Interrupt Controller Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{DMA Embedded Interrupt Controller Registers}
@include spec/dma_eic.tex
@c --------------------------------------------------------------------------
@page
@appendix Vectored Interrupt Controller
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{Vectored Interrupt Controller}
@include wb_vic.tex
@c --------------------------------------------------------------------------
@page
@appendix Time-tagging Core Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{Time-tagging Core Registers}
@include timetag_core_regs.tex
@c --------------------------------------------------------------------------
@page
@appendix SPEC Carrier Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{SPEC Carrier Registers}
@include spec/carrier_csr.tex
@c --------------------------------------------------------------------------
@page
@appendix SVEC Carrier Registers
The registers documentation have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
@anchor{SVEC Carrier Registers}
@include svec/carrier_csr.tex
@c --------------------------------------------------------------------------
@page
@appendix Glossary
@section Glossary
@table @b
@item Local bus
The @b{local bus} is the interface between the GN4124 and the FPGA.
@item Pulse
In this document, a @b{pulse} refers to a one clock tick wide pulse.
@item Tick
A clock @b{tick} corresponds to a period of the clock.
@item SDB
Self-Describing Bus
@item VIC
Vectored Interrupt Controller
@item EIC
Embedded Interrupt Controller
@end table
@bye
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#s/[^\\]%.*$//
s/^\\%/%/
#preserve blanks and braces in @example blocks
/^@example/,/^@end example/ s/{/@{/g
/^@example/,/^@end example/ s/}/@}/g
/^@example/,/^@end example/ p
/^@example/,/^@end example/ d
/^@smallexample/,/^@end smallexample/ s/{/@{/g
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@verbatim
integration: vid=0xCE42, did=0x47c786a2
wb crossbar: vid=0x0651, did=0xe6a542c9
wb bridge : vid=0x0651, did=0xeef0b198
vic : vid=0xCE42, did=0x00000013
onewire : vid=0xCE42, did=0x779c5443
spec_csr : vid=0xCE42, did=0x00000603
svec_csr : vid=0xCE42, did=0x00006603
timetag : vid=0xCE42, did=0x00000604
fmc_eic : vid=0xCE42, did=0x26ec6086
i2c : vid=0xCE42, did=0x123c5443
spi : vid=0xCE42, did=0xe503947e
adc_csr : vid=0xCE42, did=0x00000608
dma_eic : vid=0xCE42, did=0xd5735ab4
dma_ctrl : vid=0xCE42, did=0x00000601
ddr_addr : vid=0xCE42, did=0x10006611
ddr_data : vid=0xCE42, did=0x10006610
@end verbatim
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab
PCB revision
@item @code{15...4}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC_PRES}
@tab @code{X} @tab
FMC presence
@item @code{1}
@tab R/O @tab
@code{P2L_PLL_LCK}
@tab @code{X} @tab
GN4142 core P2L PLL status
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR3_CAL_DONE}
@tab @code{X} @tab
DDR3 calibration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc_pres} @tab 0: FMC slot is populated@*1: FMC slot is not populated.
@item @code{p2l_pll_lck} @tab 0: not locked@*1: locked.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr3_cal_done} @tab 0: not done@*1: done.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{LED_GREEN}
@tab @code{0} @tab
Green LED
@item @code{1}
@tab R/W @tab
@code{LED_RED}
@tab @code{0} @tab
Red LED
@item @code{2}
@tab R/W @tab
@code{DAC_CLR_N}
@tab @code{0} @tab
DAC clear
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0}
@tab @code{0} @tab
State of the reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: disable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: disable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{DMA_DONE}
@tab @code{0} @tab
DMA done interrupt
@item @code{1}
@tab W/O @tab
@code{DMA_ERROR}
@tab @code{0} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab write 1: enable interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab write 1: enable interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/O @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is enabled@*read 0: interrupt 'DMA done interrupt' is disabled
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is enabled@*read 0: interrupt 'DMA error interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{DMA_DONE}
@tab @code{X} @tab
DMA done interrupt
@item @code{1}
@tab R/W @tab
@code{DMA_ERROR}
@tab @code{X} @tab
DMA error interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{dma_done} @tab read 1: interrupt 'DMA done interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA done interrupt'@*write 0: no effect
@item @code{dma_error} @tab read 1: interrupt 'DMA error interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'DMA error interrupt'@*write 0: no effect
@end multitable
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@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- dma controller
0x1100 |-- onewire master
0x1200 |-- spec csr
0x1300 |-- vic
0x1400 |-- dma eic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c master
0x3100 | |-- spi master
0x3200 | |-- i2c master
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc-adc eic
0x3600 | |-- timetag core
@end verbatim
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab
PCB revision
@item @code{15...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC0_PRES}
@tab @code{X} @tab
FMC 1 presence
@item @code{1}
@tab R/O @tab
@code{FMC1_PRES}
@tab @code{X} @tab
FMC 2 presence
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR0_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 4 calibration status
@item @code{4}
@tab R/O @tab
@code{DDR1_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 5 calibration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_pres} @tab 0: FMC slot 1 is populated@*1: FMC slot 1 is not populated.
@item @code{fmc1_pres} @tab 0: FMC slot 2 is populated@*1: FMC slot 2 is not populated.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0}
@tab @code{0} @tab
State of the FMC 1 reset line
@item @code{1}
@tab R/W @tab
@code{FMC1}
@tab @code{0} @tab
State of the FMC 2 reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@item @code{fmc1} @tab write 0: Normal FMC operation@* write 1: FMC is held in reset
@end multitable
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@verbatim
0x0000 crossbar (sdb records)
0x1000 |-- i2c
0x1100 |-- onewire
0x1200 |-- svec csr
0x1300 |-- vic
0x2000 |-- bridge (fmc slot 1) -> crossbar (sdb records)
0x3000 | |-- i2c
0x3100 | |-- spi
0x3200 | |-- i2c
0x3300 | |-- adc csr
0x3400 | |-- onewire
0x3500 | |-- fmc_eic
0x3600 | |-- timetag
0x4000 |-- ddr_addr (fmc slot 1)
0x5000 |-- ddr_data (fmc slot 1)
0x6000 |-- bridge (fmc slot 2) -> crossbar (sdb records)
0x7000 | |-- i2c
0x7100 | |-- spi
0x7200 | |-- i2c
0x7300 | |-- adc csr
0x7400 | |-- onewire
0x7500 | |-- fmc_eic
0x7600 | |-- timetag
0x8000 |-- ddr_addr (fmc slot 2)
0x9000 |-- ddr_data (fmc slot 2)
@end verbatim
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@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{seconds_upper} @tab
Timetag seconds register (upper)
@item @code{0x4} @tab
REG @tab
@code{seconds_lower} @tab
Timetag seconds register (lower)
@item @code{0x8} @tab
REG @tab
@code{coarse} @tab
Timetag coarse time register, system clock ticks (125MHz)
@item @code{0xc} @tab
REG @tab
@code{time_trig_seconds_upper} @tab
Time trigger seconds register (upper)
@item @code{0x10} @tab
REG @tab
@code{time_trig_seconds_lower} @tab
Time trigger seconds register (lower)
@item @code{0x14} @tab
REG @tab
@code{time_trig_coarse} @tab
Time trigger coarse time register, system clock ticks (125MHz)
@item @code{0x18} @tab
REG @tab
@code{trig_tag_seconds_upper} @tab
Trigger time-tag seconds register (upper)
@item @code{0x1c} @tab
REG @tab
@code{trig_tag_seconds_lower} @tab
Trigger time-tag seconds register (lower)
@item @code{0x20} @tab
REG @tab
@code{trig_tag_coarse} @tab
Trigger time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x24} @tab
REG @tab
@code{acq_start_tag_seconds_upper} @tab
Acquisition start time-tag seconds register (upper)
@item @code{0x28} @tab
REG @tab
@code{acq_start_tag_seconds_lower} @tab
Acquisition start time-tag seconds register (lower)
@item @code{0x2c} @tab
REG @tab
@code{acq_start_tag_coarse} @tab
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x30} @tab
REG @tab
@code{acq_stop_tag_seconds_upper} @tab
Acquisition stop time-tag seconds register (upper)
@item @code{0x34} @tab
REG @tab
@code{acq_stop_tag_seconds_lower} @tab
Acquisition stop time-tag seconds register (lower)
@item @code{0x38} @tab
REG @tab
@code{acq_stop_tag_coarse} @tab
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x3c} @tab
REG @tab
@code{acq_end_tag_seconds_upper} @tab
Acquisition end time-tag seconds register (upper)
@item @code{0x40} @tab
REG @tab
@code{acq_end_tag_seconds_lower} @tab
Acquisition end time-tag seconds register (lower)
@item @code{0x44} @tab
REG @tab
@code{acq_end_tag_coarse} @tab
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
@end multitable
@regsection @code{seconds_upper} - Timetag seconds register (upper)
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{SECONDS_UPPER}
@tab @code{X} @tab
Timetag seconds
@end multitable
@regsection @code{seconds_lower} - Timetag seconds register (lower)
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{SECONDS_LOWER}
@tab @code{X} @tab
Timetag seconds
@end multitable
@regsection @code{coarse} - Timetag coarse time register, system clock ticks (125MHz)
Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{COARSE}
@tab @code{X} @tab
Timetag coarse time
@end multitable
@regsection @code{time_trig_seconds_upper} - Time trigger seconds register (upper)
8 upper bits of seconds used for timer trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{TIME_TRIG_SECONDS_UPPER}
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_seconds_lower} - Time trigger seconds register (lower)
32 lower bits of seconds used for time trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{TIME_TRIG_SECONDS_LOWER}
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_coarse} - Time trigger coarse time register, system clock ticks (125MHz)
Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{TIME_TRIG_COARSE}
@tab @code{0} @tab
Time trigger coarse value
@end multitable
@regsection @code{trig_tag_seconds_upper} - Trigger time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/O @tab
@code{TRIG_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Trigger time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_seconds_upper} @tab Holds time-tag seconds of the last trigger event
@end multitable
@regsection @code{trig_tag_seconds_lower} - Trigger time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{TRIG_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Trigger time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_seconds_lower} @tab Holds time-tag seconds of the last trigger event
@end multitable
@regsection @code{trig_tag_coarse} - Trigger time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/O @tab
@code{TRIG_TAG_COARSE}
@tab @code{X} @tab
Trigger time-tag coarse time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_tag_coarse} @tab Holds time-tag coarse time of the last trigger event
@end multitable
@regsection @code{acq_start_tag_seconds_upper} - Acquisition start time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/O @tab
@code{ACQ_START_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition start time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition start event
@end multitable
@regsection @code{acq_start_tag_seconds_lower} - Acquisition start time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_START_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition start time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition start event
@end multitable
@regsection @code{acq_start_tag_coarse} - Acquisition start time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/O @tab
@code{ACQ_START_TAG_COARSE}
@tab @code{X} @tab
Acquisition start time-tag coarse time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_start_tag_coarse} @tab Holds time-tag coarse time of the last acquisition start event
@end multitable
@regsection @code{acq_stop_tag_seconds_upper} - Acquisition stop time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition stop time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition stop event
@end multitable
@regsection @code{acq_stop_tag_seconds_lower} - Acquisition stop time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition stop time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition stop event
@end multitable
@regsection @code{acq_stop_tag_coarse} - Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/O @tab
@code{ACQ_STOP_TAG_COARSE}
@tab @code{X} @tab
Acquisition stop time-tag coarse time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_stop_tag_coarse} @tab Holds time-tag coarse time of the last acquisition stop event
@end multitable
@regsection @code{acq_end_tag_seconds_upper} - Acquisition end time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/O @tab
@code{ACQ_END_TAG_SECONDS_UPPER}
@tab @code{X} @tab
Acquisition end time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_seconds_upper} @tab Holds time-tag seconds of the last acquisition end event
@end multitable
@regsection @code{acq_end_tag_seconds_lower} - Acquisition end time-tag seconds register (lower)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{ACQ_END_TAG_SECONDS_LOWER}
@tab @code{X} @tab
Acquisition end time-tag seconds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_seconds_lower} @tab Holds time-tag seconds of the last acquisition end event
@end multitable
@regsection @code{acq_end_tag_coarse} - Acquisition end time-tag coarse time (system clock ticks 125MHz) register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/O @tab
@code{ACQ_END_TAG_COARSE}
@tab @code{X} @tab
Acquisition end time-tag coarse time
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{acq_end_tag_coarse} @tab Holds time-tag coarse time of the last acquisition end event
@end multitable
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<h1 class="heading">wb_slave_vic</h1>
<h3>Vectored Interrupt Controller (VIC)</h3>
<p>Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">VIC Control Register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Raw Interrupt Status Register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt Enable Register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Interrupt Disable Register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Interrupt Mask Register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Vector Address Register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Software Interrupt Register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">End Of Interrupt Acknowledge Register</a></span><br/>
<span style="margin-left: 0px; ">4. <A href="#sect_4_0">Memory blocks</a></span><br/>
<span style="margin-left: 20px; ">4.1. <A href="#sect_4_1">Interrupt Vector Table</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#CTL">VIC Control Register</a>
</td>
<td class="td_code">
vic_ctl
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#RISR">Raw Interrupt Status Register</a>
</td>
<td class="td_code">
vic_risr
</td>
<td class="td_code">
RISR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#IER">Interrupt Enable Register</a>
</td>
<td class="td_code">
vic_ier
</td>
<td class="td_code">
IER
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#IDR">Interrupt Disable Register</a>
</td>
<td class="td_code">
vic_idr
</td>
<td class="td_code">
IDR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#IMR">Interrupt Mask Register</a>
</td>
<td class="td_code">
vic_imr
</td>
<td class="td_code">
IMR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#VAR">Vector Address Register</a>
</td>
<td class="td_code">
vic_var
</td>
<td class="td_code">
VAR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#SWIR">Software Interrupt Register</a>
</td>
<td class="td_code">
vic_swir
</td>
<td class="td_code">
SWIR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#EOIR">End Of Interrupt Acknowledge Register</a>
</td>
<td class="td_code">
vic_eoir
</td>
<td class="td_code">
EOIR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x20 - 0x3f
</td>
<td >
MEM
</td>
<td >
<A href="#IVT_RAM">Interrupt Vector Table</a>
</td>
<td class="td_code">
vic_ivt_ram
</td>
<td class="td_code">
IVT_RAM
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>VIC Control Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ctl_enable_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[5:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ctl_pol_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ctl_emu_edge_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ctl_emu_len_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Raw Interrupt Status Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_risr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt Enable Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ier_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ier_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt Disable Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_idr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_idr_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt Mask Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_imr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Vector Address Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_var_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Software Interrupt Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_swir_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_swir_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>End Of Interrupt Acknowledge Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_eoir_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_eoir_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt Vector Table:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ivt_ram_addr_i[4:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ivt_ram_data_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
vic_ivt_ram_rd_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. VIC Control Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=3 class="td_field">
EMU_LEN[15:13]
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EMU_LEN[12:5]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=5 class="td_field">
EMU_LEN[4:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EMU_EDGE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
POL
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENABLE
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ENABLE
</b>[<i>read/write</i>]: VIC Enable
<br>- 1: enables VIC operation<br>- 0: disables VIC operation
<li><b>
POL
</b>[<i>read/write</i>]: VIC output polarity
<br>- 1: IRQ output is active high<br>- 0: IRQ output is active low
<li><b>
EMU_EDGE
</b>[<i>read/write</i>]: Emulate Edge sensitive output
<br>- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum.<br>- 0: Normal IRQ master line behavior
<li><b>
EMU_LEN
</b>[<i>read/write</i>]: Emulated Edge pulse timer
<br>Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.
</ul>
<a name="RISR"></a>
<h3><a name="sect_3_2">3.2. Raw Interrupt Status Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_risr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
RISR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RISR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RISR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RISR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RISR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
RISR
</b>[<i>read-only</i>]: Raw interrupt status
<br>Each bit reflects the current state of corresponding IRQ input line.<br>- read 1: interrupt line is currently active<br>- read 0: interrupt line is inactive
</ul>
<a name="IER"></a>
<h3><a name="sect_3_3">3.3. Interrupt Enable Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_ier
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
IER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IER[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IER[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IER[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IER[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
IER
</b>[<i>write-only</i>]: Enable IRQ
<br>- write 1: enables interrupt associated with written bit<br>- write 0: no effect
</ul>
<a name="IDR"></a>
<h3><a name="sect_3_4">3.4. Interrupt Disable Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_idr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
IDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IDR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IDR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IDR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IDR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
IDR
</b>[<i>write-only</i>]: Disable IRQ
<br>- write 1: enables interrupt associated with written bit<br>- write 0: no effect
</ul>
<a name="IMR"></a>
<h3><a name="sect_3_5">3.5. Interrupt Mask Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_imr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
IMR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IMR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IMR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IMR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
IMR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
IMR
</b>[<i>read-only</i>]: IRQ disabled/enabled
<br>- read 1: interrupt associated with read bit is enabled<br>- read 0: interrupt is disabled
</ul>
<a name="VAR"></a>
<h3><a name="sect_3_6">3.6. Vector Address Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_var
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
VAR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
VAR
</b>[<i>read-only</i>]: Vector Address
<br>Address of pending interrupt vector, read from Interrupt Vector Table
</ul>
<a name="SWIR"></a>
<h3><a name="sect_3_7">3.7. Software Interrupt Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_swir
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SWIR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<p>
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWIR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWIR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWIR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWIR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SWIR
</b>[<i>write-only</i>]: SWI interrupt mask
</ul>
<a name="EOIR"></a>
<h3><a name="sect_3_8">3.8. End Of Interrupt Acknowledge Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
vic_eoir
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EOIR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EOIR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EOIR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EOIR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EOIR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
EOIR
</b>[<i>write-only</i>]: End of Interrupt
<br>Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
</ul>
<a name="IVT_RAM"></a>
<h3><a name="sect_4_1">4.1. Interrupt Vector Table</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
vic_ivt_ram
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td >
0x20
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
IVT_RAM
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td >
0x80
</td>
</tr>
<tr>
<td >
<b>Size: </b>
</td>
<td >
32 32-bit words
</td>
</tr>
<tr>
<td >
<b>Data width: </b>
</td>
<td >
32
</td>
</tr>
<tr>
<td >
<b>Access (bus): </b>
</td>
<td >
read/write
</td>
</tr>
<tr>
<td >
<b>Access (device): </b>
</td>
<td >
read-only
</td>
</tr>
<tr>
<td >
<b>Mirrored: </b>
</td>
<td >
no
</td>
</tr>
<tr>
<td >
<b>Byte-addressable: </b>
</td>
<td >
no
</td>
</tr>
<tr>
<td >
<b>Peripheral port: </b>
</td>
<td >
bus-synchronous
</td>
</tr>
</table>
<br>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
vic_ivt_ram_addr_i[4:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
vic_ivt_ram_data_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
vic_ivt_ram_rd_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<p>Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through <code>g_init_vectors</code> generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.</p>
</BODY>
</HTML>
doc/manual/wb_vic.tex deleted 100644 → 0
View file @ f2640a29
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{CTL} @tab
VIC Control Register
@item @code{0x4} @tab
REG @tab
@code{RISR} @tab
Raw Interrupt Status Register
@item @code{0x8} @tab
REG @tab
@code{IER} @tab
Interrupt Enable Register
@item @code{0xc} @tab
REG @tab
@code{IDR} @tab
Interrupt Disable Register
@item @code{0x10} @tab
REG @tab
@code{IMR} @tab
Interrupt Mask Register
@item @code{0x14} @tab
REG @tab
@code{VAR} @tab
Vector Address Register
@item @code{0x18} @tab
REG @tab
@code{SWIR} @tab
Software Interrupt Register
@item @code{0x1c} @tab
REG @tab
@code{EOIR} @tab
End Of Interrupt Acknowledge Register
@item @code{0x20 - 0x3f}
@tab MEM @tab @code{IVT_RAM} @tab Interrupt Vector Table
@end multitable
@regsection @code{CTL} - VIC Control Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{ENABLE}
@tab @code{0} @tab
VIC Enable
@item @code{1}
@tab R/W @tab
@code{POL}
@tab @code{0} @tab
VIC output polarity
@item @code{2}
@tab R/W @tab
@code{EMU_EDGE}
@tab @code{0} @tab
Emulate Edge sensitive output
@item @code{18...3}
@tab R/W @tab
@code{EMU_LEN}
@tab @code{0} @tab
Emulated Edge pulse timer
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ENABLE} @tab @bullet{} 1: enables VIC operation@*@bullet{} 0: disables VIC operation
@item @code{POL} @tab @bullet{} 1: IRQ output is active high@*@bullet{} 0: IRQ output is active low
@item @code{EMU_EDGE} @tab @bullet{} 1: Forces a low pulse of @code{EMU_LEN} clock cycles at each write to @code{EOIR}. Useful for edge-only IRQ controllers such as Gennum.@*@bullet{} 0: Normal IRQ master line behavior
@item @code{EMU_LEN} @tab Length of the delay (in @code{clk_sys_i} cycles) between write to @code{EOIR} and re-assertion of @code{irq_master_o}.
@end multitable
@regsection @code{RISR} - Raw Interrupt Status Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{RISR}
@tab @code{X} @tab
Raw interrupt status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RISR} @tab Each bit reflects the current state of corresponding IRQ input line.@*@bullet{} read 1: interrupt line is currently active@*@bullet{} read 0: interrupt line is inactive
@end multitable
@regsection @code{IER} - Interrupt Enable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IER}
@tab @code{0} @tab
Enable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IER} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IDR} - Interrupt Disable Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{IDR}
@tab @code{0} @tab
Disable IRQ
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IDR} @tab @bullet{} write 1: enables interrupt associated with written bit@*@bullet{} write 0: no effect
@end multitable
@regsection @code{IMR} - Interrupt Mask Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IMR}
@tab @code{X} @tab
IRQ disabled/enabled
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IMR} @tab @bullet{} read 1: interrupt associated with read bit is enabled@*@bullet{} read 0: interrupt is disabled
@end multitable
@regsection @code{VAR} - Vector Address Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{VAR}
@tab @code{X} @tab
Vector Address
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{VAR} @tab Address of pending interrupt vector, read from Interrupt Vector Table
@end multitable
@regsection @code{SWIR} - Software Interrupt Register
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SWIR}
@tab @code{0} @tab
SWI interrupt mask
@end multitable
@regsection @code{EOIR} - End Of Interrupt Acknowledge Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{EOIR}
@tab @code{0} @tab
End of Interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{EOIR} @tab Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
@end multitable
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