Trigger over SATA

f79a2210 · Tristan Gingold · Federico Vaga · 15094615 · f79a2210 · f79a2210
Commit f79a2210 authored Jul 23, 2021 by Tristan Gingold Committed by Federico Vaga Jan 11, 2022
5 changed files
--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -77,6 +77,7 @@ entity fmc_adc_100Ms_core is
    trigger_tag_i   : in t_timetag;
    time_trig_i     : in std_logic;
    aux_time_trig_i : in std_logic;
+    conn_trig_i     : in std_logic := '0';  -- (not synced)
    -- WR status (for trigout).
    wr_tm_link_up_i    : in std_logic;
@@ -194,11 +195,15 @@ architecture rtl of fmc_adc_100Ms_core is
  signal aux_time_trig              : std_logic;
  signal aux_time_trig_sync         : std_logic;
  signal aux_time_trig_fixed_delay  : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
+  signal conn_trig_en               : std_logic := '1';
+  signal conn_trig                  : std_logic;
+  signal conn_trig_sync             : std_logic;
+  signal conn_trig_fixed_delay      : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
  signal trig                       : std_logic;
-  signal trig_align                 : std_logic_vector(8 downto 0);
+  signal trig_align                 : std_logic_vector(9 downto 0);
  signal trig_storage               : std_logic_vector(31 downto 0);
  signal trig_storage_clear         : std_logic;
-  signal trig_src_vector            : std_logic_vector(7 downto 0);
+  signal trig_src_vector            : std_logic_vector(8 downto 0);
  -- Down-sampling
  signal downsample_factor : std_logic_vector(31 downto 0) := (others => '0');
@@ -206,8 +211,8 @@ architecture rtl of fmc_adc_100Ms_core is
  signal downsample_en     : std_logic;
  -- Sync FIFO (from fs_clk to sys_clk_i)
-  signal sync_fifo_din   : std_logic_vector(72 downto 0);
+  signal sync_fifo_din   : std_logic_vector(73 downto 0);
-  signal sync_fifo_dout  : std_logic_vector(72 downto 0);
+  signal sync_fifo_dout  : std_logic_vector(73 downto 0);
  signal sync_fifo_empty : std_logic;
  signal sync_fifo_full  : std_logic;
  signal sync_fifo_wr    : std_logic;
@@ -863,6 +868,21 @@ begin
      data_i  => aux_time_trig_sync,
      pulse_o => aux_time_trig);
+  cmp_conn_trig_sync : gc_sync
+    port map (
+      clk_i     => fs_clk,
+      rst_n_a_i => '1',
+      d_i       => conn_trig_i,
+      q_o       => conn_trig_sync);
+  cmp_conn_trig_posedge : gc_posedge
+    port map (
+      clk_i   => fs_clk,
+      rst_n_i => '1',
+      data_i  => conn_trig_sync,
+      pulse_o => conn_trig);
  -- Internal hardware trigger
  gen_int_trig : for I in 1 to 4 generate
    int_trig_data(I) <= data_calibr_out(16*I-1 downto 16*I-16);
@@ -961,16 +981,19 @@ begin
        ext_trig_fixed_delay      <= (others => '0');
        time_trig_fixed_delay     <= (others => '0');
        aux_time_trig_fixed_delay <= (others => '0');
+        conn_trig_fixed_delay     <= (others => '0');
      else
        sw_trig_fixed_delay   <= sw_trig_fixed_delay(sw_trig_fixed_delay'high -1 downto 0) & sw_trig;
        ext_trig_fixed_delay  <= ext_trig_fixed_delay(ext_trig_fixed_delay'high -1 downto 0) & ext_trig_d;
        time_trig_fixed_delay <= time_trig_fixed_delay(time_trig_fixed_delay'high -1 downto 0) & time_trig;
        aux_time_trig_fixed_delay <= aux_time_trig_fixed_delay(aux_time_trig_fixed_delay'high -1 downto 0) & aux_time_trig;
+        conn_trig_fixed_delay <= conn_trig_fixed_delay(conn_trig_fixed_delay'high -1 downto 0) & conn_trig;
      end if;
    end if;
  end process p_trig_shift;
-  trig_src_vector <= sw_trig_fixed_delay(sw_trig_fixed_delay'high) &
+  trig_src_vector <= (conn_trig_fixed_delay(conn_trig_fixed_delay'high) and conn_trig_en) &
+                     sw_trig_fixed_delay(sw_trig_fixed_delay'high) &
                     (ext_trig_fixed_delay(ext_trig_fixed_delay'high) and ext_trig_en) &
                     aux_time_trig_fixed_delay(aux_time_trig_fixed_delay'high) &
                     (time_trig_fixed_delay(time_trig_fixed_delay'high) and time_trig_en) &
@@ -1028,7 +1051,7 @@ begin
  cmp_adc_sync_fifo : generic_async_fifo_dual_rst
    generic map (
-      g_DATA_WIDTH => 73,
+      g_DATA_WIDTH => 74,
      g_SIZE       => 16,
      g_SHOW_AHEAD => TRUE)
     port map(
@@ -1044,6 +1067,7 @@ begin
      rd_empty_o        => sync_fifo_empty);
  -- Data to FIFO
+  --     73 : conn trigger
  --     72 : sw trigger
  --     71 : ext trigger
  --     70 : aux time trigger
@@ -1054,7 +1078,7 @@ begin
  --     65 : int1 trigger
  --     64 : trigger pulse signal
  -- 63..00 : sample data
-  sync_fifo_din(72 downto 64) <= trig_align;
+  sync_fifo_din(73 downto 64) <= trig_align;
  sync_fifo_din(63 downto 0)  <= data_calibr_out_d3;
  -- FIFO control
@@ -1365,7 +1389,7 @@ begin
        trig_storage <= X"0000" &
                        X"0" & sync_fifo_dout(68 downto 65) &
                        "00" & sync_fifo_dout(70 downto 69) &
-                        "00" & sync_fifo_dout(72 downto 71);
+                        "0"  & sync_fifo_dout(73 downto 71);
      end if;
    end if;
  end process p_trig_storage_sys;

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -76,6 +76,10 @@ entity fmc_adc_mezzanine is
    wb_trigout_slave_i : in  t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
    wb_trigout_slave_o : out t_wishbone_slave_out;
+    --  Trigger (from SATA)
+    conn_trig_in_i     : in std_logic := '0';
+    conn_trig_out_o    : out std_logic;
    -- FMC interface
    ext_trigger_p_i : in std_logic;               -- External trigger
    ext_trigger_n_i : in std_logic;
@@ -339,6 +343,7 @@ begin
      trigger_tag_i   => trigger_tag,
      time_trig_i     => time_trigger,
      aux_time_trig_i => aux_time_trigger,
+      conn_trig_i     => conn_trig_in_i,
      wr_tm_link_up_i    => wr_tm_link_up_i,
      wr_tm_time_valid_i => wr_tm_time_valid_i,
@@ -365,6 +370,8 @@ begin
      gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
      gpio_si570_oe_o  => gpio_si570_oe_o);
+  conn_trig_out_o <= trigger_p;
  ------------------------------------------------------------------------------
  -- Mezzanine 1-wire master
  --    DS18B20 (thermometer + unique ID)

--- a/hdl/top/spec_sata_design/sata_controller.vhd
+++ b/hdl/top/spec_sata_design/sata_controller.vhd
@@ -8,6 +8,13 @@ entity sata_controller is
    tx_clk_i      :     std_logic;
    rx_clk_i      :     std_logic;
+    --  Got a trigger from SATA (clocked by rx_clk_i)
+    trig_out_o    : out std_logic;
+    --  Trigger to send over SATA (clocked by tx_clk_i)
+    trig_in_i     : in  std_logic;
+    --  When SATA is ready.
    rdy_i         : in  std_logic;
    --  TX
@@ -28,8 +35,12 @@ end sata_controller;
 architecture arch of sata_controller is
  signal tx_data_reg : std_logic_vector(7 downto 0);
  signal tx_data_wr : std_logic;
+  signal tx_wr_r : std_logic;
  signal rx_wr, rx_valid : std_logic;
+  signal trig_out : std_logic_vector(2 downto 0);
+  signal trig_in_sync, trig_in : std_logic;
 begin
  inst_sync_tx: entity work.gc_sync_word_wr
    generic map (
@@ -49,11 +60,62 @@ begin
      wr_o => tx_data_wr
    );
-  tx_data_o <= tx_data_reg when tx_data_wr = '1' else x"bc";
+  --  Resync trig_in
-  tx_k_o <= not tx_data_wr;
+  cmp_conn_trig_sync : entity work.gc_sync
+    port map (
+      clk_i     => rx_clk_i,
+      rst_n_a_i => '1',
+      d_i       => trig_in_i,
+      q_o       => trig_in_sync);
+  cmp_conn_trig_posedge : entity work.gc_posedge
+    port map (
+      clk_i   => rx_clk_i,
+      rst_n_i => '1',
+      data_i  => trig_in_sync,
+      pulse_o => trig_in);
+  --  TX arbiter:
+  --   First trig_in
+  --   Second tx_data (and save tx_wr pulse in case of trig_in)
+  --   Last, idle
+  process (tx_clk_i)
+  begin
+    if rising_edge(tx_clk_i) then
+      tx_wr_r <= (tx_wr_r or tx_data_wr) and trig_in;
+    end if;
+  end process;
+  process (tx_data_reg, tx_data_wr, trig_in_i)
+  begin
+    if trig_in = '1' then
+      tx_data_o <= x"f7";
+      tx_k_o <= '1';
+    elsif tx_data_wr = '1' or tx_wr_r = '1' then
+      tx_data_o <= tx_data_reg;
+      tx_k_o <= '0';
+    else
+      tx_data_o <= x"bc";
+      tx_k_o <= '1';
+    end if;
+  end process;
  rx_valid <= (not rx_k_i) and rdy_i;
+  --  Generate trig_out (extended)
+  process (rx_clk_i)
+  begin
+    if rising_edge(rx_clk_i) then
+      if rx_k_i = '1' and rdy_i = '1' and rx_data_i = x"f7" then
+        trig_out <= "111";
+        trig_out_o <= '1';
+      else
+        trig_out_o <= trig_out (0);
+        trig_out <= '0' & trig_out(2 downto 1);
+      end if;
+    end if;
+  end process;
  inst_rx_data: entity work.gc_sync_word_wr
    generic map (
      g_auto_wr => False,

--- a/hdl/top/spec_sata_design/spec_sata.vhd
+++ b/hdl/top/spec_sata_design/spec_sata.vhd
@@ -22,6 +22,9 @@ entity spec_sata is
    clk_125m_clk1_101_n_i : in   std_logic;            -- 125 MHz GTP ref (clk1 101)
    clk_125m_clk1_101_p_i : in   std_logic;
+    conn_trig_in_i        : in   std_logic;
+    conn_trig_out_o       : out  std_logic;
    -- SATA
    sata0_txp_o           : out  std_logic;
    sata0_txn_o           : out  std_logic;
@@ -40,7 +43,7 @@ end spec_sata;
 architecture arch of spec_sata is
  signal sata_rdy, sata_rx, sata_rst, sata_rst1   : std_logic_vector(1 downto 0);
-  signal sata_rx_data_rd, sata_tx_data_wr         : std_logic_vector (1 downto 0);
+  signal sata_rx_data_rd, sata_tx_data_wr         : std_logic_vector(1 downto 0);
  signal sata_rx_data0, sata_rx_data1             : std_logic_vector(31 downto 0);
  signal sata_tx_data0, sata_tx_data1             : std_logic_vector(31 downto 0);
  signal gtp_rx_data0, gtp_tx_data0               : std_logic_vector(7 downto 0);
@@ -48,6 +51,7 @@ architecture arch of spec_sata is
  signal gtp_rx_data1, gtp_tx_data1               : std_logic_vector(7 downto 0);
  signal gtp_rx_k1, gtp_tx_k1, gtp_rx_clk1        : std_logic;
  signal clk_125m_gtp123_buf, clk_125m_gtp101_buf : std_logic;
+  signal trig_in, trig_out : std_logic_vector(1 downto 0);
 begin
  inst_sata_regs: entity work.sata_regs
    port map (
@@ -154,6 +158,8 @@ begin
      rst_62m5_n_i => rst_sys_62m5_n_i,
      tx_clk_i => clk_ref_125m_i,
      rx_clk_i => gtp_rx_clk0,
+      trig_in_i => trig_in(0),
+      trig_out_o => trig_out(0),
      rdy_i => sata_rdy(0),
      reg_tx_data_i => sata_tx_data0(7 downto 0),
      reg_tx_wr_i => sata_tx_data_wr(0),
@@ -228,6 +234,8 @@ begin
      rst_62m5_n_i => rst_sys_62m5_n_i,
      tx_clk_i => clk_ref_125m_i,
      rx_clk_i => gtp_rx_clk0,
+      trig_in_i => trig_in(1),
+      trig_out_o => trig_out(1),
      rdy_i => sata_rdy(1),
      reg_tx_data_i => sata_tx_data1(7 downto 0),
      reg_tx_wr_i => sata_tx_data_wr(1),
@@ -241,6 +249,11 @@ begin
    );
  sata_rx_data1 (31 downto 8) <= (others => '0');
+  --  Trigger connections.
+  conn_trig_out_o <= trig_out(0) or trig_out(1);
+  trig_in(0) <= trig_out(1) or conn_trig_in_i;
+  trig_in(1) <= trig_out(0) or conn_trig_in_i;
  gen_chipscope: if False and g_simulation = 0 generate
    component chipscope_icon_sata
      port (

--- a/hdl/top/spec_sata_design/spec_sata_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_sata_design/spec_sata_fmc_adc_100Ms.vhd
@@ -265,6 +265,8 @@ architecture arch of spec_sata_fmc_adc_100Ms is
  signal wrabbit_en         : std_logic;
  signal pps_led            : std_logic;
+  signal conn_trig_in, conn_trig_out : std_logic;
 begin  -- architecture arch
  inst_spec_base : entity work.spec_base_wr
@@ -492,6 +494,9 @@ begin  -- architecture arch
      ext_trigger_p_i => adc_ext_trigger_p_i,
      ext_trigger_n_i => adc_ext_trigger_n_i,
+      conn_trig_in_i => conn_trig_out,
+      conn_trig_out_o => conn_trig_in,
      adc_dco_p_i  => adc_dco_p_i,
      adc_dco_n_i  => adc_dco_n_i,
      adc_fr_p_i   => adc_fr_p_i,
@@ -559,6 +564,8 @@ begin  -- architecture arch
        clk_sys_62m5_i => clk_sys_62m5,
        rst_sys_62m5_n_i => rst_sys_62m5_n,
        clk_ref_125m_i => clk_ref_125m,
+        conn_trig_in_i => conn_trig_in,
+        conn_trig_out_o => conn_trig_out,
        clk_125m_clk0_123_n_i => clk_125m_clk0_123_n_i,
        clk_125m_clk0_123_p_i => clk_125m_clk0_123_p_i,
        clk_125m_clk1_101_n_i => clk_125m_clk1_101_n_i,